Downloading the bitstream (configuring the device)

Once you have created the bitstream successfully, you can configure the FPGA or the CPLD. There are several possibilities depending on the board you are using:  the Digilab board, the FPGA Demoboard, the XS40 board for the FPGA, or the XS95 board for the CPLD. In addition, you can also do  in-circuit or in-system programming (ISP). Make sure that you have generated the bitstream corresponding to the proper device to which you want to download (XC4005E or XC4010E on the FPGA Demoboard, XC4005XL FPGA on the XS40 board and XC95108 CPLD on the XC95 board). The configuration file for the FPGA has a .bit extension and the one for the CPLD has a .svf extension. a. Using the Digilab board

i. Board Set-up

A description of the Digilab board is given in the section "Digilent Digilab Board". The board contains a Spartan XCS10XL or XCS05XL FPGA that can be programmed over a parallel cable. Check that the board is powered up and that the switch SW9 is in the PROG position (see Figure below).

Digilab board (Digilent, Inc.)

ii. Select project version and revision.

In the Project Manager window, highlight the design project you want to download and select the desired revision (in the left pane window, Versions tab) as shown in Figure 2 below.


Figure 2: Design Manager window (Screen clip from Xilinx (TM) Foundation software)

iii. Open the Hardware Debugger

Click on the Programming button in the right window pane (Flow tab) of the Project Manager. A small Select Program window will pop up: select the middle button - Hardware Debugger - and click OK.
 
 



The Hardware Debugger window will now open, shown in Figure 3 below.

Figure 3: Hardware Debugger window (Screen clip from Xilinx (TM) Foundation software)

iv. Download the bitstream

In the Hardware Debugger window, pull down the CABLE menu and select COMMUNICATIONS. This will bring up the Communications Setup windows shown below. Select the Parallel Cable and click on the OK button.

Figure 4: Communications setup window (Screen clip from Xilinx (TM) Foundation software)

Next, select DOWNLOAD menu -> DOWNLOAD DESIGN. This will initiate the downloading of the bit stream. Your device has been programmed. You are now ready to test the design.

Note: If an error occured, double check  that the design has been compiled for the right type of device. The device type for which the design has been compiled is shown in the Hardware Debugger window. Compare it with the device on the Digilab board. If the device type does not correspond to the one on your board, change it by going to the Proejct Manager and select FILE -> PROJECT TYPE. This will allow you to change the device type. If you change the type, you need to reimplement the design.
 

b. Using the Xilinx Demoboard with the XChecker cable

i. Board Set-up

A descirption of the board is given in the section "FPGA Demonstration Board". The board allows you to program the FPGA with the XChecker cable. Make sure the demoboard is powered and the XChecker cable connected properly. The configuration switches SW2 (1 through 8) should be set as described in the Xilinx FPGA DemoBoard write-up (ON - OFF - OFF - ON - ON - ON - ON - OFF). The decimal points of the two left most 7-segment displays should be "ON" at this point. Figure 1 shows a schematic figure of the demoboard,
 
 

Figure 1: FPGA Demo Board (Ref. Xilinx)





ii. Select project version and revision.

In the Project Manager window, highlight the design project you want to download and select the desired revision (in the left pane window, Versions tab) as shown in Figure 2 below.
 
 

Figure 2: Design Manager window (Screen clip from Xilinx (TM) Foundation software)



iii. Open the Hardware Debugger

Click on the Programming button in the right window pane (Flow tab) of the Project Manager. A small Select Program window will pop up: select the middle button - Hardware Debugger - and click OK.




The Hardware Debugger window will now open, shown in Figure 3 below.
 
 


Figure 3: Hardware Debugger window (Screen clip from Xilinx (TM) Foundation software)



iv. Download the bitstream

In the Hardware Debugger window, select DOWNLOAD menu -> DOWNLOAD DESIGN.

The downloading process should start. During downloading, the decimal point of the right-most 7-segment (U8) display acts as a programming error indicator. During programming the decimal point of U6 and U7 will be lit, while that of U8 should be off. When downloading is successful, the decimal point of U7 will go off and that of U6 stays lit. If a programming error occurs, the decimal point of U8 comes on.

The software will say "DONE signal went high" and will give no errors if the programming was successful. You can now start testing your design.

If an error occurred, check the XChecker cable, the power to the board, and the switch settings. In case there is a problem with the cable, go to the CABLE - > COMMUNICATIONS. In the Communications Setup select:  PORT (choose COM1), Cable Type (XChecker), Baud Rate (9600). Also, make sure that the design has been compiled for the right type of device. Check that the device type (go to the  Project Manager window and select FILE -> PROJECT TYPE) corresponds to the device on the board. If it is compiled for a device other than XC4010EPC84, choose the right one and re-implement the design.

c. Using the XS40 board.

A description of the XS40 board is given in the section "XS40 Prototyping Board".  The board can be used to program the XC4005XL FPGA through the parallel port of a PC or from the on-board EEPROM. The mode of operation depends on the jumper settings, as explained in the XS40 Board description. We will first explain how to use the parallel port to program the device (programming the on-board EEPROM is shown further on).

i. Programming the FPGA on the XS40 board through the parallel port.

Make sure that the jumpers are in their default configuration so that you can program the board through the parallel port. We will use the GXSLOAD utility to program the FPGA. The following steps will download the design from the PC in the FPGA.
 
 

Figure 4: Schematic view of the XS40 board

  1. Connect the parallel port on the board to the parallel port of the PC. Next, connect the power supply to the XS40 board.
  2. Double click on the GXSLOAD program, which is located in the xstools/bin directory. This will open the gxsload window. Select the parallel port (e.g. LPT1) and leave the EEPROM box unchecked (see Figure 5)
  3. You can now drop the bitstream file of the design you want to download into the window. This is done by going to the directory in which you stored your design (e.g. C:\MY_DIR\MY_PROJ\) and selecting the configuration file, my_proj.bit. Drag and drop the  my_proj.bit file into the "gxsload window". The download process will begin.

    Figure 5: GXSLOAD window for programming the FPGA through the parallel port.
    (Screen clip from the XESS GXSTools).

You can now start testing your design. Test signals are applied through the parallel cable using the GXSPORT utility (in the XSTOOLS/BIN directory, click on GXSPORT) shown in Figure 6. In the GXSPORT window, set the value of the data bits corresponding to the input signals as defined in the user constraint file. Lets assume that you assigned the following pin numbers:  DOOR (P44), IGNITION (P45) and SBELT (P46) which correspond to ports D0, D1 and D2, respectively (see XS40 board - Table 2 - parallel port). Assume that output BUZZER (P19) has been connected to Pin 19 which corresponds to LED segment "a" on the XS40 board. Go through the various input combinations and check the corresponding output. The LED should go on when D1(=Ignition)  is "1" and D0 (=Door) or D2 (=Seatbelt) are "0". If you check off the Count box every time you click on the strobe button, the counter will advance by one bit.

Figure 6: GXSPORT window for applying test signals through the parallel port.





In case you do not have the GXSLOAD program, you can give the load command in a DOS window as follows:

C:\> XSLOAD my_proj.bit
You may have to give the full pathname for your project or change to your project directory before issuing the xsload command. You can use the same command to download an Intel-formatted HEX file into the SRAM on the XS40 board:
C:\> XSLOAD my_file.hex
or
C:\> XSLOAD my_file.hex my_proj.bit


NOTE: you can download the XSTOOLs from the XESS Corp. website. Once you have  saved the xstooset.exe file on your PC, double click it. The set-up program will create a XSTOOLS\BIN directory which contains the GXS utitilies to program the FPGA on the XS board (gxsload.exe), to set the on-board clock (gxssetclk.exe), to test the XS board (gxstest.exe) and to apply test signals to the board (gxsport.exe).

ii. Storing the configuration file in the EEPROM on the XS40 board

You can also store your design in the on-board non-volatile EEPROM. As soon as you power on the board, the FPGA will be configured from the PROM and is ready to be used, without having to program it from the parallel port. This is convenient once you have finalized your design. In order to store the configuration file on the PROM, you will need to add an EEPROM in socket 7 of the XS40 board and set a few jumpers. Use an AT17C256 Atmel reprogrammable serial EEPROM in the event you want to store the configuration files for the XS4005 or XS4010 FPGAs. Follow these steps to load the design in the Atmel EEPROM.

  1. Turn off the power to the XS40 board
  2. Place the EEPROM (AT17C256) chip in socket U7.
  3. Shunt jumper J6.
  4. Reapply power to the board
  5. Start the GXSLOAD program. In the gxsload window, check off the EEPROM box and drag and drop the bitstream file (e.g. my_proj.bit)  you want to download in the EEPROM (see Figure 5). This bitstream file can be found in your project directory. As soon as you drop the file in the gxsload window, the programming will start. It will take about a minute or less to program the EEPROM.
  6. Turn off the power to the board
  7. Remove the shunt on jumper J6.
  8. In order for the XS40 board to download the configuration file stored in the EEPROM into the FPGA upon power on, you still need to set a few jumpers as follows.
    1. First remove the parallel cable from port J1 on the XS40 board (this is needed so that the mode pins 32 and 34 of the FPGA are at logic 0 which is needed to power up in the active-serial mode).
    2. Shunt jumper J10 in order to set the FPGA in the active-serial mode so that it can be loaded from the EEPROM
    3. Remove the shunts on jumpers J4 and J11.
    4. Reapply power to the XS40 board. The FPGA will now be configured from the serial EEPROM. You can now connect the cable back to the parellel port connect J1 so that you can apply test signals using the GXSPORT program.


d. Using the XS95 board.

We will use the GXSLOAD utility to program the CPLD. Make sure that the jumpers have their default settings as explained in the section "XS95 Prototyping Board".
 
 

Figure 7: Schematic view of the XS95 board.





Before you can download the bitstream in a CPLD you need to translate the bitstream generated by the Flow Engine into a format that is suitable for the CPLD device. This is an extra step that was not needed for a FPGA. If you haven't done this step yet, do it now. Once you have generated the right file (.svf),  download the design (.svf file) from the PC in the CPLD on the XS95 board as follows:.

  1. Connect the parallel port on the board to the parallel port of the PC. Next, connect the power supply to the XS95 board.
  2. Double click on the  GXSLOAD program, which is located in the xstools/bin directory. This will open the gxsload window (see Figure 4). Select the parallel port (e.g. LPT1) and leave the EEPROM box unchecked.
  3. You can now drop the configuration file of the design you want to download into the window. This is done by going to the directory in which you stored your design corresponding to the version and revision you would like to download (e.g. C:\MY_DIR\MY_PROJ\XPROJ\Ver\Rev) and selecting the configuration file, my_proj.svf. Drag and drop the  my_proj.svf  file into the "gxsload window". The download process will begin. This may take several seconds.
You can now start testing your design. Since the CPLD has a non-volatile memory that stores its configuration file, the configuration will be restored as soon as the power is applied to the XS95 board. Of course, you can always overwrite the stored configuration file using the programming procedure described above.

In case you do not have the GXSLOAD program, you can give the load command in a DOS window as follows:

C:\> XSLOAD my_proj.svf
You may have to give the full pathname for your project or change to your project directory before issuing the xsload command. You can use the same command to download an Intel-formatted HEX file into the SRAM on the XS95 board:
C:\> XSLOAD my_file.hex
or
C:\> XSLOAD my_file.hex XSLOAD my_proj.svf


NOTE: you can download the XSTOOLs from the XESS Corp. website. Once you have  saved the xstooset.exe file on your PC, double click it. The set-up program will create a XSTOOLS\BIN directory which contains the GXS utitilies to program the FPGA on the XS board (gxsload.exe), to set the on-board clock (gxssetclk.exe), to test the XS board (gxstest.exe) and to apply test signals to the board (gxsport.exe).
 

Back to the Foundation Tutorial table of Contents
Go to tutorial: Entering a Schematic | Entering a design with ABEL  | Entering a design with VHDL| Simulation | Macros and Hierarchical design | State Editor  |  Design Implementation | Configuring a device  | Common Mistakes |
Board description: FPGA Demoboard | XS40 | XS95 |
Pinouts: XC4000 | XC9500.

Copyright 1999, Jan Van der Spiegel. Created by Jan Van der Spiegel <jan@ee.upenn.edu>; August 27, 1997; Updated August 5, 2001