A - B - C - D - E - F - G - H - I - J - K - L - M - N - O - P - Q - R - S - T - U - V - W - X - Y - Z

A

Assertion errors
- Running and debugging the simulation

B

Batch-mode simulation
- Lesson 5 - Running a batch-mode simulation

Breakpoints
- Running the simulation

continuing simulation after
- Running the simulation

C

Code Coverage
- Lesson 9 - Simulating with Code Coverage

coverage_summary window
- Running a simulation with Code Coverage

reload
- Merging coverage results from two simulations

report
- Running a simulation with Code Coverage

vsim -coverage command
- Running a simulation with Code Coverage

Command history
- Command history

compare

icons
- Compare icons

Compile

compile order
- Preparing the simulation

compile order of Verilog modules
- Preparing the simulation

mixed HDL design
- Preparing the simulation

Verilog
- Preparing the simulation

coverage_summary window
- Running a simulation with Code Coverage

D

Debugging a VHDL design
- Lesson 4 - Debugging a VHDL design

Design

create new library
- Preparing the simulation

Design library

create new
- Preparing the simulation

creating
- Preparing the simulation

do command
- Reusing commands from the Main transcript

DO files

executing a DO file in batch-mode
- Lesson 5 - Running a batch-mode simulation

using a DO file at startup
- Lesson 6 - Executing commands at startup

using the transcript as a DO file
- Reusing commands from the Main transcript

documentation
- Introduction

drag and drop
- Drag and drop

E

Errors

breaking on assertion
- Running and debugging the simulation

finding in VHDL designs
- Running and debugging the simulation

viewing in Source window
- Running and debugging the simulation

examine command
- Debugging the simulation

examples

Tcl example solutions
- Solutions to the examples

F

Find dialog box
- Finding items by name in tree windows

Finding

a cursor in the Wave window
- Finding a cursor

Finding names, and searching for values
- Lesson 8 - Finding names and values

force command
- Running the simulation

H

Hierarchical Profile
- Running the simulation

update icon
- Speeding up the simulation

Hierarchy

of a mixed VHDL/Verilog design
- Running the simulation

of a Verilog design
- Preparing the simulation

I

IEEE std 1076
- Standards supported

IEEE std 1364
- Standards supported

K

Keyboard shortcuts, Wave window
- Keyboard shortcuts for zooming

L

Libraries

creation and mapping
- Preparing the simulation

logical mapping
- Preparing the simulation

List window

change display radix
- Debugging the simulation

placing top level Verilog signals in
- Preparing the simulation

Load Design
- Running the simulation

Load design
- Preparing the simulation

M

Macros
- Reusing commands from the Main transcript

P

Performance Analyzer
- Lesson 10 - Simulating with the Performance Analyzer

hierarchical profile
- Running the simulation

ranked profile
- Speeding up the simulation

report command
- Speeding up the simulation

profile on command
- Running the simulation

Project files

create
- Creating a Project

Q

quit VSIM command
- Running the simulation
- Debugging the simulation

R

Ranked Profile
- Speeding up the simulation

reference signals
- Lesson 10 - Comparing waveforms

report command
- Speeding up the simulation

restart
- Debugging the simulation
- Running and debugging the simulation

Reusing commands
- Reusing commands from the Main transcript

Run length selector

change run length
- Preparing the simulation

run VSIM command
- Running the simulation

S

Searching

for HDL item names and transitions in the Wave window
- Zooming - changing the waveform display range

for values and finding names in windows
- Lesson 8 - Finding names and values

in tree windows
- Finding items by name in tree windows

Shortcuts

command history
- Command history

Wave window
- Keyboard shortcuts for zooming

Signal transitions

searching for
- Zooming - changing the waveform display range

Signals

add to List window
- Preparing the simulation

add to Wave window
- Preparing the simulation

applying stimulus to
- Running the simulation

display values with examine command
- Debugging the simulation

listing in region
- Preparing the simulation

placing top-level Verilog signals in the List and Wave window
- Preparing the simulation

specifying radix of
- Changing new-line triggering

triggering listings for
- Changing new-line triggering

Simulating

code coverage
- Lesson 9 - Simulating with Code Coverage

with Performance Analyzer
- Lesson 10 - Simulating with the Performance Analyzer

Simulation

batch-mode
- Lesson 5 - Running a batch-mode simulation

executing commands at startup
- Lesson 6 - Executing commands at startup

Load Design dialog box
- Preparing the simulation

mixed VHDL/Verilog
- Lesson 4 - Mixed VHDL/Verilog simulation

saving results in log file
- Lesson 5 - Running a batch-mode simulation

single-stepping
- Running the simulation

starting
- Preparing the simulation

Verilog
- Lesson 3 - Basic Verilog simulation

-view switch
- Lesson 5 - Running a batch-mode simulation

-wlf switch
- Lesson 5 - Running a batch-mode simulation

Software updates
- Introduction

solutions to the examples
- Solutions to the examples

Standards supported
- Standards supported

Support
- Introduction

System initialization file
- Lesson 6 - Executing commands at startup

T

Tcl/Tk

how it works with ModelSim
- How Tcl/Tk works with ModelSim

Tcl source command
- The Tcl source command

Tk widgets
- Tk widgets

Technical support
- Introduction

test signals
- Lesson 10 - Comparing waveforms

Transcript

save
- Reusing commands from the Main transcript

transcript DO file
- Make a transcript DO file

Triggering

changing in List window
- Changing new-line triggering

modify
- Changing new-line triggering

U

Updates
- Introduction

V

Verilog

compile
- Preparing the simulation

interface checking between design units
- Preparing the simulation

viewing design in Structure and Source windows
- Running the simulation

Verilog simulation
- Lesson 3 - Basic Verilog simulation

view_profile command
- Running the simulation

vsim -coverage command
- Running a simulation with Code Coverage

W

Wave window

placing top level Verilog signals in
- Preparing the simulation

Waveform Comparison

icons
- Compare icons

reference signals
- Lesson 10 - Comparing waveforms

test signals
- Lesson 10 - Comparing waveforms

Windows

finding HDL item names
- Lesson 8 - Finding names and values

searching for HDL item values
- Lesson 8 - Finding names and values

List window

locating time markers
- Lesson 8 - Finding names and values

viewing all
- Preparing the simulation

Wave window

changing display range (zoom)
- Zooming - changing the waveform display range

cursor measurements
- Making cursor measurements

locating time cursors
- Lesson 8 - Finding names and values

using time cursors
- Using time cursors in the Wave window

zooming
- Zooming - changing the waveform display range

Work library mapping
- Preparing the simulation

Z

Zoom

from Wave toolbar buttons
- Zooming with the toolbar buttons

from Zoom menu
- Zooming - changing the waveform display range

with the mouse
- Zooming with the mouse

Zooming in the Wave window
- Zooming - changing the waveform display range

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