EE 8273 VLSI Systems I, Fall 2002


This is the home page for VLSI Systems I (also known as VLSI II) course for the Fall 2002 semester. 'Intro to VLSI Design' (VLSI I, EE4253) is a prerequisite for this course. The object of this course is to discuss system aspects of VLSI design; we will be concentrating on the design of larger blocks such as RAMS and datapaths as well as design techniques such as dynamic logic.

Textbook

I will use the textbook used in EE 4253 (Principles of CMOS VLSI Design , Weste) and Digital Integrated Circuits , Rabaey.

Tools

The principle simulation tool will be Cadence Spectre for transistor level simulation. We will also use Modelsim for Verilog gate level simulation.

Near the end of the semester we WILL look at block placement/routing tools from Cadence.

EMAIL List

The class EMAIL list will be the one provided by Information Technology Services (ITS). The email list for this class is ece8273-01.fall2002@courses.msstate.edu . See the Class EMAIL Faq for further information about how to be added to the list.

Policy

The grading policy will be:


All external assignments are to be INDIVIDUAL work. You may discuss the assignments with other students but you may not share any work, or show anybody your work as examples of how to do something. Any violations of this policy will result in the assignment of a failing grade for the ENTIRE course.

Topics

Topics that we will be covering include:

  1. Brief review of static CMOS Design
  2. Review of HSPICE -- characterization of delay, power, and input capacitance
  3. Dynamic Logic design styles, particularly Domino Logic
  4. Clock tree design
  5. Delay optimization
  6. Memory Design
  7. PLA design
  8. CAD Tool flows

Links to Course Information

I will be placing lecture notes in Powerpoint format here. Many of these notes are taken from David Harris, Harvey Mudd College (see High Speed CMOS Circuit Design ) and one of the authors of the book "Logical Effort: Designing Fast CMOS Circuits" (other authors are Ivan Sutherland, Bob Sproull). Another note source is Borivoje Nikolic, Berkeley (see Advanced Digital Integrated Circuits ).

Erik Brunvand's (University of Utah) Advanced IC Design course page has some very good notes/tutorials on Cadence usage and IC design.

Lectures for Fall 2002

Old Tests

Old Lectures from Fall 2001

Old Lectures from Fall 2000

Assignments Fall 2002

Assignments will be posted here.

  1. Delay Prediction Homework, due September 5 class time , ZIP Archive , Submission Script.
  2. Delay Optimization Homework, due September 17 class time , Perl Script for Fall 01 semester assignment , Submission Script.
  3. Simple Pipelined System , Due Sept 26, Oct 3rd, ZIP Archive , Update to Pipelined System Homework , Submission Script.
  4. Domino Pipeline Homework , ZIP archive of ALU RTL model for Domino Pipe System, Submission Script.

Project, Fall 2002

Project information posted here.

  1. Project Definition , Zip Archive of VHDL for FIFO for Project Default , Example FIFO: Cypress Synchronous FIFO , Perl script for testing sequence generators
  2. Due Dates. November 7th: screenshot of some standard cell layout you have produced, Novemember 14th: Verilog gate level model, December 1,Midnight: Project due.
  3. Submission Script, Screenshot.
  4. Submission Script, Gate Level Simulation.

Old, Assignments Fall 2001

Assignments will be posted here.

  1. Delay Prediction Homework, due September 7, class time , SOLUTION , Submission Script. Submission must be a directory called 'sim1' which contains a report file called 'report.pdf'. Download the script, and execute it via 'perl submit_ee8273_sim1.pl'; your directory will be archived and emailed to you and myself (be sure to check that you recieve a copy of the email - if you do not, then resubmit). You can submit multiple times, I only look at the last submission. Place all supporting spice source files, spreadsheets, etc in this directory as well (and I *do* want to see your spice source files). Please specify in the report how the spice files were used. I do not want any spice trace files or measurement files.
  2. Delay Optimization Homework, due September 14th, class time , SOLUTION , Submission script, Alternate Submission script.
  3. Pass transistor Logic, Charge Sharing: due September 21, class time , SOLUTION , Submission script
  4. 4-bit ALU in Domino Logic, due October 19th, class time , ZIP archive with testbench files , Submission script
  5. Fall 2001 Project, due December 2nd, midnight , Sample Interface , VHDL File

Old Assignments

Perl

Below is an introduction lecture to Perl. Many VLSI/ECAD engineers find Perl or similar scripting languages very useful in small programming tasks that they are faced with. I would strongly suggest that you take the time to learn Perl or something similar - it will make you a more efficient VLSI/ECAD engineer.

  • Introduction to Perl , PDF

    Modelsim, Verilog

    Misc Links

    Cadence Spectre Notes

    This semester we will be using Cadence Spectre for transistor level simulations. I will post some Powerpoint notes on Cadence Spectre and you can also use the Cadence Online help system. The Spectre Reference manual, User Manual, Verilog-A reference are available in PDF form under ~reese/cadence_docs (I cannot post these on the Web, but you can view them from any ECE machine).