A

<+/-> <Inverted or Non-Inverted> clock path from clock <name> to destination has <high or low> pulse width of <time>

<+/-> <Latch or Launch> edge is <time>

<+/-> <Longest or Shortest> <register or pin> to <register or pin> delay is <time>

<+/-> <Longest or Shortest> <register or pin> to <register or pin> requirement is <time>

<+/-> <Longest or Shortest> clock path from clock <name> to <source or destination> <register or memory> is <time>

<+/-> <Longest or Shortest> clock skew is <time>

<+/-> External delay of pin is <time>

<+/-> Hold relationship between source and destination is <time>

<+/-> Micro clock to output delay of source is <time>

<+/-> Micro hold delay of destination is <delay>

<+/-> Micro setup delay of destination is <time>

<+/-> Offset between input clock <name> and output clock <name> is <time>

<+/-> Register <name> has a <high or low> minimum pulse width requirement of <time>

<+/-> Setup relationship between source and destination is <time>

<+/-> tco from clock to output pin is <time>

<+/-> tco requirement for source <register or memory> and destination pin is <time>

<+/-> th from clock to input pin is <time>

<+/-> th requirement for source pin and destination <register or memory> is <time>

<+/-> tsu from clock to input pin is <time>

<+/-> tsu requirement for source pin and destination <register or memory> is <time>

<command> - Incorrect number of arguments. Should be <arglist>.

<Hexadecimal (Intel-format) Output File, Programmer Object File, Raw Binary File, or Tabular Text File> programming file type does not support selected programming mode

<input, output, or bidirectional> pin <name> at <pin> uses the <name> I/O standard and consumes <number> uA of static current

<Longest or Shortest> tpd from source pin <name> to destination pin <name> is <time>

<name> assigned to LogicLock region <name>

<name> used during last compilation -- new SignalProbe assignment ignored

<path element number>: + <increment delay> = <total delay>; Loc. = <location name>; <node type> Node = '<node name>'

<text>

<text>

<text>

<text>

<text>

<text>

<type> fmax is <number> (period= <number>) for register <name>

<type> fmax is restricted to <number> (period= <time>) for register <name>

A file with the same name as the VHDL or Verilog Design File already exists. Do you want to overwrite the file?

A LAB legality constraint could not be satisfied: <name>

A LogicLock region named <name> already exists in the project -- assigning unique name <name> to new region

Acquiring post-trigger data

Acquiring pre-trigger data

Acquisition in progress

Acquisition in progress

Adapter not recognized

Adapter not recognized

Add nodes to the current instance

Adder direction error: illegal value <text> for <name> parameter

Address line changed on Embedded System Block <ESB name> during port B write cycle at time <time> -- simulation results may be incorrect

Address line changed on Embedded System Block <name> during port A write cycle at time <time> -- simulation results may be incorrect

Address line changed on Embedded System Block <name> during write at time <time> -- simulation results may be incorrect

ads.cshrc has not been sourced

AHDL feature (<text>) not currently supported

AHDL Include File <name> already exists. Do you want to overwrite the INC File?

Alias <name> already exists. Do you want to replace the signals for the new alias with the ones from <name>?

Alias <name> already exists. Do you want to replace the signals for the new alias with the ones from <name>?

All data inputs of SERDES transmitter <name> must be synchronized to the core clock

All dedicated SERDES receivers driven by the fast PLL <name> must have the same dynamic phase alignment mode

All dedicated SERDES transmitters or receivers driven by the fast PLL <name> must have the same data width

All destination nodes of output pin <name> of PLL <name> constrained to region <name>

All differential I/O pins driven by fast PLL <name> must have same I/O standard

All differential I/O SERDES receivers that are driven by fast PLL <name> have CORE_CLK input frequency of <number> MHz, but frequency must be <number> MHz

All differential I/O SERDES receivers that are driven by fast PLL <name> must have same CORE_CLK input port source

All DQ I/O pins driven by DQS I/O pin <name> must be driven by same clock

All output drivers between two GNDIO pins cannot sink current that exceeds <number>mA maximum

All output drivers between two GNDIO pins sink current exceeding <number>mA maximum

All output drivers between two GNDIO pins sink current exceeding 273mA maximum

All outputs of SERDES receiver <name> must be synchronized to the core clock

All pins were used during last compilation -- new SignalProbe assignment(s) not available

All pins were used during last compilation -- new SignalProbe assignment(s) not available

All pins were used during last compilation -- new SignalProbe assignment(s) not available

All timing requirements were met. See Report window for more details.

aload port and apre port cannot be connected at same time in LCELL ATOM <name>

aload port and apre port cannot be connected at the same time in WYSIWYG LCELL primitive <name>

aload port and apre port cannot be connected at the same time in WYSIWYG primitive <name>

Already using <number> dedicated clock pins

Already using <number> dedicated fast pins

Already using <number> regular I/O pins

Already using Compiler settings name -- do you want to overwrite existing Compiler settings?

Already using dedicated fast pin <name> for internal global signal

Already using Simulator settings name -- do you want to overwrite existing Simulator settings?

Already using software build settings name -- do you want to overwrite existing software build settings?

Altera recommends manually setting trigger nodes allocated to take advantage of the incremental route feature. Do you want the nodes allocated to match the current number of nodes used?

Altera recommends removing all location assignments when changing the device -- do you want to remove all location assignments?

Altera recommends removing all location assignments when changing the device. Do you want to remove all location assignments? Removing all location assignments will also remove all I/O standard assignments.

Analysis and elaboration have not been performed on the current project. The Quartus II software may not be able to automatically locate all project files. Do you want to continue anyway?

Analysis and elaboration were <successful, NOT successful, stopped, or canceled due to an error>

Analysis and elaboration were not performed on the current project. The Quartus II software may not be able to automatically locate all project files.

Analysis of design file <name> was <successful, NOT successful, stopped, or canceled due to an error>

Annotating netlist with estimated timing delays

Another set of routing constraints encountered for signal <name> on line <number>. To finish routing, the Quartus II software will disregard this set of routing constraints.

Archive directory <name> does not exist. Do you want to create it?

areset input port of GXB transmitter PLL <name> must be driven by pllresetout output port of XGMII state machine atom

areset port and sreset port cannot be connected at same time in WYSIWYG I/O primitive <name>

Argument <name> for USED function is not a pin or a parameter

Argument for LOG2 cannot be negative number or zero

Arithmetic expression cannot compare a number to a quoted string

Arithmetic expression cannot contain denominator value of zero

Arithmetic expression cannot contain divisor of zero

Arithmetic expression cannot contain quoted string <text>

Arithmetic expression contains node or group name(s) <name(s)>, but only Boolean expressions can contain nodes and groups

ARM-based Excalibur signal <name> cannot be assigned to pin -- signal not available in current device

Assembler or C/C++ compiler cannot compile software source file <name>

Assembler or C/C++ compiler cannot compile software source file <name> when command-line command is specified to run during software build

Assembler or C/C++ compiler compiled software source file <name>

Assert Statement message string uses <number> message variables, but uses only <number> variables

Assertion error: <text>

Assertion information: <text>

Assertion warning: <text>

Assign a Programmer Object File to the POF Data item

Assigned <name> is 0, but must be a positive number greater than 0. Using default fmax requirement.

Assigned I/O standard <name> as default I/O standard for current project, but I/O standard is not supported for the chosen device family

Assigned I/O standard <name> as default I/O standard for current project, but I/O standard is not supported for the current device

Assigned I/O standard <name> to node <name>, but I/O standard is not supported for the current device

Assigned node <name> to dedicated fast pin <name>

Assigned node <name> to location <name>

Assigned node <name> to LogicLock region <name>

Assigned node <name> to LogicLock region <name>

Assignment <name> is a negative number or zero, but must be a positive number

Assignment <name> is a negative number or zero, but must be a positive number. Assignment will be ignored

Assignment <name> is not supported

Assignment <name>=<name> on location <name> cannot be moved to location <name> because it conflicts with existing assignment <name>=<name>

Assignment comment: <text>

Assignment destination node: <name>

Assignment ignored: <Yes/No>

Assignment may contain error -- <text>

Assignment of node <name>, which feeds input port of type <type> of <LVDS transmitter PLL> <name>, to pin <name> is illegal

Assignment of single-ended I/O pin <name> to HSDI I/O bank is illegal when HSDI receiver or transmitter is used

Assignment of single-ended I/O pin <name> to I/O bank <number> is illegal when dynamic phase aligners are enabled in SERDES receivers

Assignment of single-ended pin <name> to HSDI I/O bank is illegal when HSDI I/O bank contains HSDI pins

Assignment option: <type>

Assignment source node: <name>

Assignment value <text> is illegal -- ignoring the setting

Assignment value <text> is illegal -- selecting the default value

Assignment value: <text>

Assignments changed outside the Assignment Editor. Do you want to save changes before reloading assignments, possibly overwriting some or all of the external changes?

Assignments reloaded -- assignments updated outside Assignment Editor

Assuming node <name> is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.

Assuming node <name> is an undefined clock

Asynchronous clear source error: illegal value <text> for <name> parameter

Asynchronous clock domain interface structure <number> contains <number> node(s)

Asynchronous clock domain interface structure <number> contains <number> node(s)

Asynchronous clock domain interface structure <number> contains <number> node(s)

Asynchronous load structure <number> contains <number> node(s)

Asynchronous reset at time <time> on write enable register of memory segment <name> is illegal

At least 1 or more bits of Port A write address on Embedded System Block <name> is already being written to by Port B at time <time> -- data will be invalid in ESB

At least one group of Compiler settings must be specified for the project before opening the Timing wizard

At least one group of Compiler settings must be specified for the project before you can run the Simulator Settings wizard

Atom <name> cannot use combinatorial output port <name> when DDIO_MODE parameter is set to INPUT or BIDIR

ATOM <name> cannot use multout port when in non-multiplier mode

ATOM <name> cannot use multsela port when in a non-multiplier mode

ATOM <name> cannot use multselb port when in a non-multiplier mode

ATOM <name> has a clear port connection without a clock signal

ATOM <name> has a clock enable without a clock signal

ATOM <name> has an extra clear port connected

ATOM <name> has an extra clock connected

Atom <name> has DDIO_MODE parameter set to INPUT or BIDIR, but does not have required registered output port

ATOM <name> has pexpin port that contains <number> unused Pterm cell(s)

ATOM <name> has port <name> that cannot be connected <text>

Atom <name> has port <name> that must be connected <text>

Atom <name> has port <name> that should be connected <text>

ATOM <name> has register control signals connected, but it does not have register

ATOM <name> must have clk port

ATOM <name> uses a register, but the ATOM has no dataout or fanout port from the register

Attempted to access JTAG server -- internal error code <number> occurred

Attempted to add user-defined device to JTAG server -- internal error code <number> occurred

Auto SLD Node Entity <name> cannot connect port <name> to destination <name> with multiple inputs

Auto SLD Node Entity <name> does not support connecting port <name> to source <name> with multiple outputs. The preferred output is selected.

Auto SLD Node Entity <name> port <name> already driven by signal <name>, cannot be driven by <name>

Auto SLD Node Entity <name> port <name> drives input signal <name> that is already driven

Auto SLD Node Entity section <name> cannot connect input port <name> with macrofunction <name>

Auto SLD Node Entity section <name> cannot connect output port <name> with macrofunction <name>

Auto SLD Node Entity section <name> has no inputs

Auto SLD Node Entity section <name> has no outputs.

Auto SLD Node Entity Section <name> in the Compiler Settings File does not contain a source file specification

Auto SLD Node Entity section <name> is missing destination signal <name>

Auto SLD Node Entity section <name> is missing enable status. Disable section by default.

Auto SLD Node Entity section <name> is missing input signal <name>

Auto SLD Node Entity section <name> is missing the keyword assignment

Auto SLD Node Entity section <name> must connect to pin <name>, but pin <name> is a primitive

Auto SLD Node Entity section <name> name duplicates name of another entity

Auto-sized LogicLock region <name> cannot be locked

Auto-sized LogicLock region <name> cannot have locked location

Auto-sized LogicLock region <name> has child LogicLock region <name> with locked location

AUTO_SLD_HUB_ENTITY section cannot be enabled without an instance name -- disabling debug hub

AUTO_SLD_HUB_ENTITY section in the Compiler Settings File does not contain a source file specification

Automatically promoted signal <name> to use <type>

Automatically promoted some destinations of signal <name> to use <type>

Automatically selected device <name> for design <name>

B

Back-annotation available for all assignments only. Do you want to back-annotate all assignments?

Base number <number> cannot contain digit <character>

BIDIR pin <name> cannot be assigned more than one value. Created single value from multiple values, but single value cannot be used.

BIDIR pin <name> does not have a source

Bidirectional I/O pin <name> cannot have differential I/O standards

Bidirectional pin <name> missing source

Bidirectional pin <name> missing source

Bidirectional pin <name> with Series setting for Termination logic option will have degraded signal integrity when driven by device without far-end termination

Bit-slice <name> of pin <name> missing source

Blank-Check failed on device

Blank-Check failed on device <number>

Blank-checking device <number>

Blank-checking device(s)

BLAST software error: <text>

BLAST software information: <text>

BLAST software warning: <text>

Block <name> at line number <number> of System Build Descriptor File <name> cannot be used because the block does not have a recognized type or is in an incorrect hierarchical position

Block Design File <name> already exists. Do you want to overwrite it?

Block I/O <name> does not exist on block <name> of instance <name>

Block I/O signal in mapping does not exist on block

Block name conflicts with name of primitive symbol

Block name conflicts with name of primitive symbol

Block or parameter <text> at line number <number> in System Build Descriptor File <name> cannot be specified more than once in block

Block or symbol <name> of instance <name> overlaps another block or symbol

Block or symbol of type <name> and instance <name> overlaps another pin, block, or symbol

Block Symbol File <name> already exists. Do you want to overwrite the file?

Block Symbol File generation was <successful, NOT successful, stopped, or canceled due to an error>

Block type <name> for WYSIWYG RAM primitive <name> is not supported in target device family

Board delay between clock output and feedback pins must be zero or greater -- assuming zero delay through board

Board delay is larger than <limit>ns

Boolean expression contains evaluated function <name>, but only arithmetic expressions can contain evaluated functions

Boot data file does not contain any memory initialization data

Both PCI I/O logic option and I/O standard <name> cannot be assigned for pin <name>

Both read enable clear and read address clear asserted during port A read cycle at time <time> on read logic register of Embedded System Block memory segment <ESB name>

Both read enable clear and read address clear asserted during port B read cycle at time <time> on read logic register of Embedded System Block memory segment <name>

Both read enable clear and read address clear asserted during read cycle at time <time> on read logic register of Embedded System Block memory segment <name>

Bottom Boot Data item and Main Block Data item can each contain only one Hexadecimal (Intel-Format) File

Breakpoint <name> has a syntax error -- <text>

Breakpoint <name> is illegal

Breakpoint time <time> is illegal

Bus contains incompatible signal names -- <name> and <name>

Bus name allowed only on bus line -- pin <name>

Bus name allowed only on bus line -- signal <name>

Bus port <name> specified in vector source file has ports with indices that do not fall in the range of port <name>[<number>:<number>] in top level design of Quartus II project

Bus port <name> specified in vector source file has width of <number> which does not match width <number> of top level port by same name

Bus range <value> is illegal in signal <name>

Bus range for signal <name> must be a number

Bus signal <name> not in conduit, which contains only signal <name>

Buses connected to instance <name> are not named - if you want to create a primitive array, you must name all nodes and buses

C

Can export files in the RAM Initialization File format, but cannot read them. Do you want to export the file as a RAM Initialization File?

Can export files in the Verilog Value Change Dump File format, but cannot read them. Do you want to export the file as a Verilog Value Change Dump File?

Can implement specified clock multiplication and clock division parameters, but not specified PHASE_SHIFT parameters for ClockLock PLL <name>

Can implement specified clock multiplication and clock division parameters, but not specified PHASE_SHIFT parameters for ClockLock PLL <name>

Can implement specified clock multiplication, clock division, and/or specified PHASE_SHIFT parameters for ClockLock PLL <name>

Can't <blank-check or verify> device number <number>

Can't access JTAG chain

Can't access programming hardware <name>

Can't achieve minimum setup and hold requirement <text> along <number> path(s). See Report window for details.

Can't achieve requested Fast Row Interconnect delay of <number> for node <name> -- achieved delay of <number>

Can't achieve requested value <number> for clock output <name> of parameter <name> -- achieved value of <number>

Can't achieve requested value <number> of parameter <name> -- achieved value of <number>

Can't achieve required parameters CLOCK<number>_BOOST = <number> and CLOCK<number>_DIVIDE = <number> for HSDI PLL <name>

Can't achieve timing requirement <text> along <number> path(s). See Report window for details.

Can't acquire data -- reconnect communications cable and device

Can't acquire data -- select correct communications cable and device

Can't acquire data -- stop other activity on the communications cable and circuit board

Can't acquire data for all of the specified instances

Can't acquire data from unknown node instance <name> with manufacture ID <id> and node type ID <id>

Can't acquire data multiple times on SignalTap II instance <name> when acquiring data from multiple instances simultaneously

Can't add file <name> to SOF Data

Can't add global option <name> to Slave Binary Image File

Can't add JTAG server <name> -- JTAG server already exists in servers list

Can't add multiple HEX files to <Main Block Data or Bottom Boot Data> item

Can't add or change assignment -- Entity Settings File <name> is read-only

Can't add peripheral <name> to register base address <text> in Slave Binary Image File

Can't add selected device <name> to device chain when in current device mode

Can't add some files from file <name> to the Quartus II Archive File

Can't allocate memory required -- terminating compilation

Can't analyze file -- file <name> is missing

Can't assign clock settings <name> to <name> GXB receiver channel output

Can't assign I/O node <name> of type <name> in LogicLock region <name> to location <name>

Can't assign instance name <name> to location <name>

Can't assign LVDS node <name> as an open-drain, bidirectional, or tri-stated output

Can't assign LVDS node <name> as an open-drain, bidirectional, or tri-stated output

Can't assign LVDS node <name> to pin <name> -- VCCIO of I/O bank for pin has already been set to a different voltage

Can't assign negative cell <name> with differential I/O standard to negative pin <name> because negative pin <name> has another I/O cell assignment

Can't assign node <name> in LogicLock region <name> to location <name> -- can't find location

Can't assign node <name> of type <type> to I/O pin <name> of type <type>

Can't assign node <name> to index <name> -- node is type <name> and the location assignment is type <name>.

Can't assign node <name> to location <name> -- can't find location

Can't assign node <name> to location <name> -- node is type <name>

Can't assign node to VREF pin <name> because pin uses an I/O standard that conflicts with I/O standard assigned to I/O bank at that location, or already has an entity or node assigned to it

Can't assign node to VREF pin <name> because pin uses an I/O standard that conflicts with I/O standard assigned to I/O bank at that location, pin location already has an entity or node assigned to it, or the pin location is invalid

Can't assign nodes to all non-differential I/O standard pins

Can't assign nodes to all non-differential I/O standard pins

Can't assign pin <name> to non-bonded pin location <name>

Can't assign pin <name> to occupied pin location <name>

Can't assign positive cell <name> and negative cell <name> with differential I/O standards to positive pin <name> and negative pin <name>

Can't assign VREF-dependent nodes to all GTL+, SSTL-2, SSTL-3, AGP, and CTT pins

Can't assign VREF-dependent nodes to all GTL+, SSTL-2, SSTL-3, HSTL, AGP-1x, and AGP-2x pins

Can't automatically fit RAM

Can't autosize children of region <name> to fit inside it

Can't back-annotate assignments

Can't back-annotate contents of LogicLock region <name> because region has Soft property turned on

Can't back-annotate contents of LogicLock region <name> without compiling the design

Can't back-annotate origin of LogicLock region <name> without compiling the design

Can't back-annotate pin assignments because pin-out information for devices with preliminary support is subject to change

Can't build application -- Software Build Settings File <name> is missing

Can't carry out device migration because selected device list contains uninstalled device <name>

Can't change origin of LogicLock region <name> -- target device is an Auto device

Can't choose best encoding method for state machine <name>

Can't close project while a process is in progress

Can't close the SignalTap II Logic Analyzer while acquisition is in progress

Can't compare the current waveform file to <name>

Can't compensate output pin <name>

Can't compile design -- design error: <text>

Can't compile design -- resynthesis output netlist or TCL Script File not generated by the PALACE software

Can't compile design -- Verilog Design File(s) specify only initial values for port <name>, and do not contain any logic

Can't compile design containing encrypted file <name> -- current license does not allow this file to be opened

Can't compile EDIF Input File due to syntax error <text>

Can't compile or simulate design -- Compiler Settings File <name> is missing or contains errors

Can't compile project with SignalTap II File -- no device is specified for the project

Can't compile project with SignalTap II instance <name> in unsupported SignalTap II IP version <number>. Current SignalTap II IP version is <number>.

Can't compile project with SignalTap II instance <name> in unsupported SignalTap II IP version <number>. Current SignalTap II IP version is <number>.

Can't compress boot data because of insufficient available memory for decompression

Can't configure device. Expected JTAG ID code 0x<number> for device <number>, but found JTAG ID code 0x<number>.

Can't connect <name> to <name> directly -- both signals are output signals

Can't connect addnsub1 port when NUMBER_OF_MULTIPLIERS parameter has value <number> -- value must be greater than or equal to 2

Can't connect addnsub3 port when NUMBER_OF_MULTIPLIERS parameter has value <number> -- value must be greater than or equal to 2

Can't connect input port <name>[<number>] of GXB receiver channel atom <name> because <text>

Can't connect pre-synthesis node source <name> for SignalTap II incremental routing

Can't connect to the Altera web site to check for updates -- check your Internet connection and/or browser settings

Can't connect TRI or OPNDRN primitive <name> to pin <name> because it is already connected to bidirectional pin <name>

Can't connect TRI or OPNDRN primitive <name> to pin <name> because it is already connected to bidirectional pin <name>

Can't continue processing -- expected file <name> is missing

Can't continue simulation because Delay Annotator information for design is missing

Can't convert CLKLOCK primitives to ClockLock PLLs -- ClockLock PLLs not supported in target device family

Can't convert SRAM Object File <name>. Check System tab (Messages window) for details.

Can't convert target device to HardCopy device

Can't convert time-limited SOF into POF, HEX File, TTF, or RBF

Can't correctly generate vector output file <name>

Can't create archive directory <name>

Can't create archive extraction directory <name>

Can't create assignment -- can't write to settings and configuration file

Can't create assignment -- can't write to settings and configuration file <name>

Can't create assignment -- one or more settings and configuration files are read-only

Can't create database directory for project in project directory <name>

Can't create directory <name>

Can't create directory <name> for output file

Can't create enough VREF pins

Can't create HDL Design File because <name> primitive <name> is missing necessary signal(s)

Can't create HDL Design File because LATCH primitive <name> is missing signal(s)

Can't create HDL Design File because TRI primitive <name> missing signal(s)

Can't create Hexadecimal (Intel-Format) Output File for EPC16 -- invalid Programmer Object File

Can't create initial placement for LogicLock regions

Can't create Jam File, Jam Byte-Code File, Serial Vector Format File, or In System Configuration File <name>. See System tab (Messages window) for details.

Can't create list file

Can't create location assignments in MegaLAB for some nodes fed by adjacent LVDS receiver <name>. LVDS performance may not meet specifications.

Can't create location assignments in MegaLAB for some nodes fed by adjacent LVDS transmitter <name>. LVDS performance may not meet specifications.

Can't create LogicLock region -- target device is an Auto device from the Mercury device family

Can't create or overwrite file <name>

Can't create or overwrite file <name>

Can't create path-based assignment source <name> destination <name> -- current device is from the Mercury device family

Can't create project in specified directory

Can't create Quartus II Archive File <name>

Can't create resynthesis constraint files -- can't access current Quartus II project directory

Can't create Serial Vector Format File for device <name>

Can't create symbol for entity <name> -- declaration for port <name> cannot be of complex type

Can't create symbol or include file -- file <name> is a BDF or compatible file

Can't create Tcl toolbar button -- all available Tcl toolbar buttons are configured. Do you want to overwrite the last Tcl toolbar button configured with Tcl command <text>?

Can't create Tcl toolbar button -- Tcl command and arguments exceed <number> characters

Can't create Verilog Quartus Mapping File <name> in project directory

Can't create Verilog Quartus Mapping File <name> in project directory

Can't create VHDL Design File or Verilog Design File -- file <name> is not a Block Design File or compatible file

Can't create VREF pin <name> because it already exists

Can't create VREF pin <name> because it already exists

Can't create VREF pin <name> because it lacks a location assignment

Can't create VREF pin <name> because it lacks a location assignment

Can't create VREF pin <name> because it lacks I/O standard assignment

Can't create VREF pin <name> because it lacks I/O standard assignment

Can't create VREF pin <name> because there is no available memory

Can't create VREF pin <name> because there is no available memory

Can't create VREF pins necessary for device migration

Can't create working directory <name>

Can't define signal <name> as both clock signal and SignalTap II signal -- removing duplicate

Can't delete -- no tables exist

Can't delete an instance while acquisition is in progress

Can't determine whether entity <name> is LVDS receiver PLL or LVDS transmitter PLL

Can't display Fitter placement -- current target device assignment is different from last compilation device

Can't display state machine states -- register holding state machine bit <name> was synthesized away

Can't divide expression by zero

Can't duplicate GXB transmitter PLL <name> because its clock input pin <name> is assigned to dedicated GXB transmitter PLL clock input pin location in device

Can't duplicate logic when timing-driven compilation options are turned off

Can't duplicate node <name> -- node belongs to a carry chain

Can't duplicate node <name> -- node belongs to a cascade chain

Can't duplicate node <name> -- node directly drives a clock signal

Can't duplicate node <name> -- node does not exist

Can't duplicate node <name> -- node is not a logic cell

Can't duplicate node <name> -- node is part of a SERDES receiver or transmitter

Can't duplicate node <name> -- node is set to Don't Touch

Can't duplicate node <name> -- node is set to Never Allow

Can't duplicate SignalProbe node <name>

Can't duplicate source node <name> -- no path exists between source node and destination node <name>

Can't duplicate virtual I/O node <name>

Can't edit selected assignment <name> with the Assignment Organizer dialog box -- assignment type not supported for target device family

Can't edit SignalProbe assignments while a compilation is in progress

Can't enable debug hub for SignalTap II Logic Analyzer without an entity name -- disabling debug hub

Can't estimate HardCopy fmax for any clocks in design

Can't export assignments to file <name> in current project directory -- specify a different directory

Can't export data to file <name>

Can't export LogicLock region assignments before performing analysis and elaboration

Can't export RAM Initialization File <name> -- file must contain at least one memory word

Can't feed gate <name> of type <type> with CASCADE primitive <name>

Can't feed gate primitive <name> with CASCADE primitive <name> because it is already fed by CASCADE primitive <name>

Can't feed logic gate <name> of type <type> by tri-state signal

Can't feed NOT gate <type> <name> by tri-state signal

Can't feed XOR gate <name> with CASCADE primitive <name>

Can't find <name> clock settings in project

Can't find a definition for parameter <name> -- assuming <value> was intended to be a quoted string

Can't find a FLEX 6000 device that meets the Compiler settings specifications, which include the specified default I/O standard

Can't find an inherited or default value for parameter <name> -- specify a parameter value

Can't find any paths of type <type> between source node <name> and destination node <name>

Can't find auto-select clock for virtual pin <name> -- setting clock to GND

Can't find Block Symbol File for block <name> -- if the file exists, it is not located in the Altera-provided or user-defined libraries

Can't find Block Symbol File for symbol <name> -- if the file exists, it is not located in the Altera-provided or user-defined libraries

Can't find bus signal in conduit

Can't find clock settings <name> in current project

Can't find clock settings <name> in current project -- ignoring clock settings

Can't find common child LogicLock region for nodes in clique <name>

Can't find Compiler settings <name> in the Compiler Settings File. These settings are needed for simulation.

Can't find corresponding PADIO pin for WYSIWYG I/O primitive <name>

Can't find corresponding PADIO pins for the following WYSIWYG I/O primitives

Can't find database file <name>

Can't find database file <name>

Can't find definition <text> for type <type> in EDIF Input File

Can't find definition of model <IBIS model name> in IBIS model files

Can't find design entity <name>

Can't find design file <name>

Can't find device database

Can't find device that meets Compiler settings specifications

Can't find device that meets specifications - choosing an appropriate device from the available devices

Can't find executable file <name>

Can't find file <name>

Can't find file <name>

Can't find file <name>

Can't find file <name>

Can't find file <name>

Can't find file <name>

Can't find file <name>

Can't find file <name>

Can't find fit

Can't find fit

Can't find fit

Can't find fit for clique assignment <name> pf type <type> -- ignoring clique assignment

Can't find function <name> in DLL <name>

Can't find IBIS model file <name>

Can't find IBIS RLC values in IBIS model files for device <name> with package <name> and pin count <number>

Can't find instance name <name> in Compiler Settings File <name>

Can't find instance name <name> in current floorplan view

Can't find JTAG Server

Can't find legal location for node <name> of type <type>

Can't find legal locations for <number> of the <type> slice(s) in design

Can't find license for core <name>

Can't find location <name> in current floorplan view

Can't find mapping for bus in block of type <name> of instance <name>

Can't find mapping for conduit in block of type <name> of instance <name>

Can't find mapping for node in block of type <name> of instance <name>

Can't find MAX+PLUS II Assignment and Configuration File <name>

Can't find MEMBER_OF assignment on oterm <name>

Can't find Memory Initialization File or Hexadecimal (Intel-Format) File <name> -- setting all initial values to 0

Can't find message location

Can't find name for bus

Can't find node <name> for functional simulation. Ignored vector source file node.

Can't find node <name> in design

Can't find node <name> in netlist

Can't find node <name> in Simulator setting <name>

Can't find node in Last Compilation floorplan

Can't find or create section <name> in settings and configuration file <name>

Can't find peripheral <name> at register base address <text> in Slave Binary Image File

Can't find pre-synthesis source node <name> for SignalTap II incremental routing

Can't find project directory <name>

Can't find signal in vector source file for input pin <name>

Can't find SignalProbe assignments -- restoring original placement and routing

Can't find SignalProbe information -- perform a smart compilation before routing SignalProbe signals

Can't find Simulator settings <name>

Can't find software build settings <name> in Software Build Settings File

Can't find software tool <name>

Can't find software toolset <name> -- specify directory for software toolset

Can't find SOPC Builder

Can't find specified vector source file <name>

Can't find stored database information -- perform a smart compilation before using the SignalProbe feature

Can't find stored device database information -- perform a smart compilation before routing SignalProbe signals

Can't find test bench file <name>

Can't find text <text>

Can't find text <text>

Can't find text <text> in current view. Do you want to switch floorplan views?

Can't find text <text> in the current device. Do you want to search in other devices?

Can't find uPCore Transaction Model Input File <name> for simulation of embedded processor core

Can't find valid I/O pin for I/O cell <name> driven by I/O cell <name>

Can't find vector source file <name>

Can't fit <number> registers in device

Can't fit design in device

Can't fit design in device

Can't fit design in device

Can't fit design in device <name> specified in System Build Descriptor File <name>

Can't fit design in device -- following <number> routing resource(s) needed by more than one signal during the last fitting attempt

Can't fit design in device -- LAB <name> requires <number> macrocells, but the LAB can contain only <number> macrocells

Can't fit design in device -- LAB <name> requires <number> pins, but the LAB can contain only <number> pins

Can't fit design in device -- LAB <name> requires <number> programmable interconnect arrays, but the LAB can contain only <number> PIAs

Can't fit design in device -- LAB <name> requires <number> shareable expanders, but the LAB can only contain <number> shareable expanders

Can't fit design in device -- nodes in regions on the device require more global signals than are available

Can't fit design in device -- retrying with increased optimization, which may result in a longer processing time

Can't fit design in device due to routing congestion

Can't generate <name> file for more than one programming file

Can't generate Binary File <name>

Can't generate boot data file <name>

Can't generate design file <name>

Can't generate design file -- document is not saved or a project is not opened

Can't generate file -- file <name> contains time-limited cores

Can't generate flash or passive programming files because System Build Descriptor File <name> does not exist

Can't generate flash programming file <name>

Can't generate flash programming file because Slave Binary Image File <name> does not exist, or does not contain configuration data for the programmable logic device portion of an ARM-based Excalibur device

Can't generate Hexadecimal (Intel-Format) File <name>

Can't generate IBIS Output File for board analysis

Can't generate IBIS Output File for device family <name>

Can't generate Library File <name>

Can't generate Motorola S-Record File <name>

Can't generate netlist output file -- top-level design entity has ports of unsupported type

Can't generate netlist output files -- compile project successfully before generating output netlists

Can't generate netlist output files because the license for encrypted files is not available

Can't generate output Binary File, Hexadecimal (Intel Format) File, Library File, or Motorola S-Record File because file directory and name is missing

Can't generate output netlist files -- compile project successfully before generating output files

Can't generate output netlist file <name> -- output netlist files are read-only

Can't generate passive programming files

Can't generate passive programming files because programmable logic Partial SRAM Object File <name> does not exist, or does not contain configuration data for the programmable logic device portion of an ARM-based Excalibur device

Can't generate Pin-Out File and floorplan package views relative to the largest SameFrame device -- option is turned off

Can't generate programming files for project because design file <name> is encrypted. It does not have license file support that allows generation of programming files.

Can't generate RAM Initialization File <name> from MIF or HEX file -- data word's radix at address <number> not converted properly

Can't generate resynthesis output files -- can't access resynthesis\adt directory in the current project directory

Can't generate resynthesis output files -- can't write to resynthesis\adt directory in the current project directory

Can't generate resynthesis output files -- cannot write to resynthesis\adt directory in the current project directory

Can't generate resynthesis output files -- current project directory is resynthesis\adt directory

Can't generate resynthesis output files -- device family <name> is not supported

Can't generate resynthesis output files -- settings and configuration file <name> does not exist

Can't generate test bench files -- analyze and elaborate the project successfully before generating test bench files

Can't generate test bench files -- compile project successfully before generating test bench files

Can't generate test bench files -- select a valid simulation tool

Can't generate test bench template files -- compile project successfully before generating test bench template files

Can't generate test bench template files -- compile project successfully before generating test bench template files

Can't generate timing closure data -- device family not supported in the Quartus II LeonardoSpectrum TimeCloser flow

Can't generate Verilog Output File, VHDL Output File, or other output files for third party tools -- specify a simulation or timing analysis tool

Can't implement <name> parameter in PLL <name> because counter is set to bypass mode

Can't implement <name> signal or parameter for PLL <name> because SCAN_CHAIN parameter is set to SHORT

Can't implement both Fast Output Register and Fast Input Register options on bidirectional pin <name> -- Fast Output Register option is default

Can't implement CASCADE primitive <name> -- polarity of CASCADE primitives and other primitives in cascade chain are inconsistent

Can't implement clique or cascade or carry chain -- node <name>, assigned by the user to position <name>, and node <text>, assigned by the Compiler to position <text>, belong to the same user clique or carry or cascade chain but have conflicting assignments

Can't implement clique or cascade or carry chain -- node <name>, assigned to location <name> and node <text>, assigned to location <text>, belong to the same clique or carry or cascade chain but have conflicting location assignments

Can't implement CLK<number>_MULTIPLY_BY parameter with value <number> and CLK<number>_DIVIDE_BY parameter with value <number> for GXB transmitter PLL <name>

Can't implement clock multiplication and clock division parameter values for PLL <name>

Can't implement GXB receiver channel atom <name> with cruclk input frequency <number> and serial clock output frequency <number>

Can't implement in ROM

Can't implement in ROM -- DFF primitive <name> is a buried register or contains conflicting control signals

Can't implement in ROM -- hierarchy has <number> inputs

Can't implement in ROM -- hierarchy is too simple

Can't implement in ROM -- input pin <name> feeds more than one DFF primitive

Can't implement in ROM -- node <name> of type <type> is not supported

Can't implement in ROM -- output pin <name> is fed by VCC or GND

Can't implement LCELL atom <name> -- LCELL atom is part of cyclic register cascade chain

Can't implement local routing assignment from I/O cell <name> to logic cell <name> due to resource conflicts in the logic cell

Can't implement local routing assignment from logic cell <name> to I/O cell <name> because the logic cell is not placed adjacent to the I/O cell

Can't implement option(s) assigned to entity <name> due to bidirectional connections between hierarchies

Can't implement option(s) assigned to entity <name> due to netlist optimizations using Fitter timing information

Can't implement option(s) assigned to entity <name> due to tri-state connections between hierarchies

Can't implement PLL <name>

Can't implement PLL <name> of type <name> -- current design requires different PLL type

Can't implement PLL because <text>

Can't implement PLL with delay chain setting values

Can't implement port <name> for enhanced PLL <name> -- SCAN_CHAIN parameter of enhanced PLL <name> is set to SHORT

Can't implement pre-divider for GXB transmitter PLL <name> because clock input does not feed from pin

Can't implement register packing on logic cell <name>

Can't implement register packing on nodes or entities assigned to location <name>

Can't implement specified clock multiplication and clock division parameters for ClockLock PLL <name>

Can't implement specified clock multiplication or division parameters for ClockLock PLL <name>

Can't implement Technology Mapper logic option due to netlist optimizations using Fitter timing information

Can't implement Technology Mapper logic option due to netlist optimizations using Fitter timing information

Can't import assignments from MAX+PLUS II Assignment and Configuration File <name>

Can't import assignments from MAX+PLUS II Assignment and Configuration File <name>

Can't import LogicLock region assignments -- Entity Settings File <name> is read-only

Can't import LogicLock region assignments before performing analysis and elaboration

Can't incrementally route SignalTap II pre-synthesis nodes

Can't initialize design to a stable state. At least one input of Node <name> has an oscillation. Check the design.

Can't initialize programming hardware setup. Make sure Altera ByteBlaster Driver is installed.

Can't insert symbol into Block Design File <name> because the symbol represents the current Block Design File

Can't interpret register <name> from System Build Descriptor File because <text>

Can't invoke Programmer to configure device

Can't launch debugger <name>

Can't launch debugger -- cannot locate debugger executable <name> for software toolset <name>

Can't launch debugger -- cannot locate Executable and Linkable Format File <name>

Can't launch debugger -- output file name not specified

Can't launch debugger -- toolset directory not specified for software toolset <name>

Can't launch debugger when using custom build software toolset

Can't launch debugger when using library output file format

Can't launch EDA synthesis tool -- project does not contain design files

Can't launch EDA synthesis tool or EDA synthesis tool generated an error

Can't launch simulation tool

Can't list timing paths for minimum delay timing analysis

Can't list timing paths for minimum delay timing analysis

Can't load and/or run Tcl Script File <name> failed while loading and/or executing

Can't load Programmer Object File in POF Data item -- all pages are filled

Can't load Programmer Object File in POF Data item -- POF contains unknown device <name>

Can't locate current focus entity -- no focus entity specified

Can't locate current focus entity in design file

Can't locate design file for entity <name>

Can't locate design file that contains the current focus entity

Can't locate Library Mapping File

Can't locate node <name>

Can't locate node or entity because Cross-Reference File <name> contains illegal design name <name>

Can't locate programming file <name> in Chain Description File <name>

Can't locate top-level file in hierarchy

Can't lock auto-sized LogicLock region <name>

Can't lock location of LogicLock region <name> -- target device is an Auto device

Can't make DQS I/O assignment -- pin <name> must be bidirectional

Can't make location assignments for members of DDR pin group driven by system clock <name> and meet DQS I/O pin placement requirements

Can't make LogicLock region <name> child of LogicLock region <name> -- resources inside region <name> do not match the resources required by back-annotated nodes in region <name>

Can't make LogicLock region <name> child of LogicLock region <name> because region <name> is bigger than region <name>

Can't make SignalTap II incremental routing connection -- cannot find node <name> in post-synthesis netlist

Can't make SignalTap II incremental routing connection -- cannot find node <name> in post-synthesis netlist

Can't make SignalTap II incremental routing connection -- output pin <name> cannot be used as a SignalTap II output pin for node <name>

Can't make SignalTap II incremental routing connection -- output pin <name> cannot be used as a SignalTap II output pin for node <name>

Can't make SignalTap II incremental routing connection -- source node <name> cannot be found

Can't make SignalTap II incremental routing connection -- source node <name> cannot be found

Can't make SignalTap II incremental routing connection -- source node <name> cannot be used in SignalTap II incremental routing connections

Can't make SignalTap II incremental routing connection -- source node <name> cannot be used in SignalTap II incremental routing connections

Can't make SignalTap II incremental routing connection -- source node <name> has multiple non-clock fan-in

Can't make SignalTap II incremental routing connection -- source node <name> has multiple non-clock fan-in

Can't make SignalTap II incremental routing connection -- source node <name> has no fan-in

Can't make SignalTap II incremental routing connection -- source node <name> has no fan-in

Can't make SignalTap II incremental routing connection -- target node <name> has multiple fan-out

Can't make SignalTap II incremental routing connection -- target node <name> has multiple fan-out

Can't make SignalTap II incremental routing connection -- target node <name> has no fan-out

Can't make SignalTap II incremental routing connection -- target node <name> has no fan-out

Can't make SignalTap II incremental routing connection for node <name> -- cannot find specified output pin

Can't make SignalTap II incremental routing connection for node <name> -- cannot find target output pin

Can't make SignalTap II incremental routing connection for node <name> -- there are no more available output pins on the device.

Can't make SignalTap II incremental routing connection for node <name> -- there are no more available output pins on the device.

Can't make SignalTap II incremental routing connection from node <name> -- target node is not a device output pin or SignalTap II node

Can't make SignalTap II incremental routing connection from node <name> -- target node is not a device output pin or SignalTap II node

Can't make SignalTap II incremental routing connection from node <name> to node <name> -- target node is an existing non-peripheral node

Can't make SignalTap II incremental routing connection from node <name> to node <name> -- target node is an existing non-peripheral node

Can't make SignalTap II incremental routing connection to output pin <name> -- pin not reserved as a SignalProbe output pin

Can't make SignalTap II incremental routing connection to output pin <name> -- pin not reserved as a SignalProbe output pin

Can't map design hierarchy <name> to product term logic because hierarchy contains LUTs

Can't map to alias <name>

Can't merge transmitter-only fast PLL <name> and receiver-only fast PLL <name>

Can't migrate currently selected target device to selected migration device -- turned off device migration

Can't migrate device -- location assignment on pin <name> cannot be migrated

Can't monitor the following nodes

Can't move assignments because of conflicting location assignments

Can't move LogicLock region <name> to origin <location> -- at this location, region exceeds bounds of target device

Can't move LogicLock region <name> to origin <location> -- at this location, region would exceed bounds of its parent LogicLock region

Can't move LogicLock region <name> to origin <location> -- device resources at this location don't match resources required by region's back-annotated nodes

Can't move LogicLock region <name> to origin <location> -- LogicLock regions for the current device cannot extend onto pins

Can't move LogicLock region <name> to selected origin -- origin must be a LAB or ESB location

Can't name block <name> because the name represents the current Block Design File

Can't name block <name> because the name represents the current Block Design File

Can't name logic function <name> of instance <name> -- function has same name as current design file

Can't open a Routing Constraints File -- routing will continue without constraints

Can't open AHDL Include File <name>

Can't open Assign Pins dialog box -- target device does not support SignalProbe assignments

Can't open Cross-Reference File <name>

Can't open current focus entity -- Compiler settings or Simulator settings not specified

Can't open current focus entity -- open a project

Can't open database file <name>. Database error: <text>

Can't open database file <name>. Database error: <text>

Can't open DLL <name>

Can't open EDIF Input File <name>

Can't open encrypted file <name> -- encrypted file does not have license file support

Can't open encrypted file <name> -- license file support for this file includes compilation support, but does not include viewing support

Can't open file <file name>. Files created in MAX+PLUS II (DOS version) and earlier are not supported

Can't open file <name>

Can't open file <name>

Can't open file <name>

Can't open file <name>

Can't open file <name>

Can't open file <name>

Can't open file <name>

Can't open file <name>

Can't open file <name> -- error reading file

Can't open file <name> -- file contains no memory cell values

Can't open file <name> as file type <type> -- attempting to open the file with default file type instead

Can't open file <name> for additions to or removals from the Quartus II Archive File (.qar)

Can't open file <name> for output

Can't open file <name> for reading

Can't open file <name> for writing

Can't open file <name> for writing

Can't open file <name>. Files created in MAX+PLUS II (DOS version) and earlier are not supported.

Can't open file <name>. See System tab (Messages window) for details.

Can't open HardCopy HC20K Power Calculator page on Altera web site -- compile the current design

Can't open HardCopy HC20K Power Calculator page on Altera web site -- current design does not contain any clock domains

Can't open HardCopy HC20K Power Calculator page on Altera web site -- Power Estimator cannot estimate power consumption for HardCopy designs with current target device

Can't open Library Mapping File <name>

Can't open or write to System Build Descriptor File <name>

Can't open programming file <name> -- not valid <type> file

Can't open project -- device support not installed

Can't open Quartus II Archive File <name>

Can't open read-only file <name>

Can't open selected entity

Can't open settings and configuration files

Can't open Simulation Report window

Can't open Simulation Report window while simulation is in progress

Can't open Text-Format or HTML-Format Report File <name>

Can't open the encrypted file <name> because there is no license file support

Can't open vector source file <name> because absolute time <time> came after <time> in Pattern Section

Can't open vector source file <name> because it contains an illegal stop time

Can't overwrite vector inputs with simulation outputs. Waveform file does not exist or is read-only.

Can't pack cells assigned to logic cell <name>

Can't pack LABs

Can't pack logic cell <name> to I/O pin <name> -- not a logic cell

Can't pack logic cell <name> to input pin <name> -- logic cell does not contain a register

Can't pack logic cell <name> to input pin <name> -- logic cell does not contain a register

Can't pack logic cell <name> to pin <name> -- logic cell does not contain a register

Can't pack memory map control register. Base address of memory region must be multiple of memory region size.

Can't pack memory map control register. Size of memory region must be more than minimum size of 16K (0x4000).

Can't pack more than two nodes in one logic cell

Can't pack node <name> and node <name> as a fast register pair because I/O cell is a dedicated I/O pin

Can't pack node <name> and node <name> as a fast register pair because of clock enable signal violation

Can't pack node <name> and node <name> as fast register pair because logic cell is illegal for I/O register packing

Can't pack node <name> and node <name> as fast register pair because no registers remain available for I/O cell

Can't pack node <name> and node <name> as fast register pair because nodes have conflicting location assignments

Can't pack node <name> and node <name> as fast register pair because of asynchronous clear signal violation

Can't pack node <name> and node <name> as fast register pair because of clock signal violation

Can't pack node <name> and node <name> as fast register pair because of synchronous clear signal violation

Can't pack node <name> and node <name> as fast register pair because one of nodes must be a logic cell and one must be an I/O cell

Can't pack node <name> and node <name> as fast register pair because one or both nodes have fast register logic option turned off

Can't pack node <name> and node <name> as fast register pair because register is in QFBK mode

Can't pack node <name> as a fast register

Can't pack nodes in design that have been back-annotated by LogicLock to the same logic cell location

Can't pack nodes in logic cell because combinatorial cell has more than three inputs

Can't pack non-peripheral register <name> to bidir I/O pin <name> -- output register and TRI or OPNDRN primitives cannot both fan-out

Can't pack non-peripheral register <name> to I/O node <name> -- all input, output, and output enable registers within a pin with preset or clear signals must come from the same source (that is, a pin or other type of logic)

Can't pack non-peripheral register <name> to I/O node <name> -- clock enable signal source of non-peripheral register is different from output and output enable register clock signals

Can't pack non-peripheral register <name> to I/O node <name> -- clock signal source of non-peripheral register is different from output and output enable register clock signals

Can't pack non-peripheral register <name> to I/O node <name> -- input, output, or output enable registers cannot have both preset and clear signals

Can't pack non-peripheral register <name> to I/O node <name> -- output and output enable registers within a pin must have same clock signal source (that is, a pin or other type of logic)

Can't pack non-peripheral register <name> to I/O node <name> -- output register and output enable register of a pin must have the same clock signal

Can't pack non-peripheral register <name> to I/O node <name> -- polarity and inversion of clock enable signal of register and I/O node are inconsistent

Can't pack non-peripheral register <name> to I/O node <name> -- polarity and inversion of clock signal of register and I/O node are inconsistent

Can't pack non-peripheral register <name> to I/O node <name> -- polarity and inversion of preset or clear signals of register and I/O node are inconsistent

Can't pack non-peripheral register <name> to I/O node <name> -- polarity and inversion of preset or clear signals of the specified register and I/O node are inconsistent

Can't pack non-peripheral register <name> to I/O node <name> -- polarity and inversion of the clock signal of the specified register and I/O node are inconsistent

Can't pack non-peripheral register <name> to I/O node <name> -- sources of preset or clear signals of register and I/O node are different

Can't pack non-peripheral register <name> to I/O pin <name> -- constant signal at clock or clear port does not match signal on I/O pin

Can't pack non-peripheral register <name> to I/O pin <name> -- pin does not drive data input port of register

Can't pack non-peripheral register <name> to I/O pin <name> -- pin does not drive data input port of register

Can't pack non-peripheral register <name> to I/O pin <name> -- pin does not drive data input port of register

Can't pack non-peripheral register <name> to I/O pin <name> -- register has a conflicting logic cell assignment

Can't pack non-peripheral register <name> to I/O pin <name> -- register has a conflicting logic cell assignment

Can't pack non-peripheral register <name> to I/O pin <name> -- register has a conflicting logic cell assignment

Can't pack non-peripheral register <name> to I/O pin <name> -- register is in packed register mode

Can't pack non-peripheral register <name> to I/O pin <name> -- register is not in normal mode

Can't pack non-peripheral register <name> to I/O pin <name> -- register is not in normal mode

Can't pack non-peripheral register <name> to I/O pin <name> -- register is not in normal mode

Can't pack non-peripheral register <name> to I/O pin <name> -- register is part of product term logic or an embedded cell

Can't pack non-peripheral register <name> to I/O pin <name> -- register is part of product term logic, an embedded cell or an I/O pin

Can't pack non-peripheral register <name> to I/O pin <name> -- register requires a preset in an I/O cell

Can't pack non-peripheral register <name> to I/O pin <name> -- register requires a preset in an I/O cell

Can't pack non-peripheral register <name> to I/O pin <name> -- register requires a preset in an I/O cell

Can't pack non-peripheral register <name> to I/O pin <name> -- register uses an asynchronous preset

Can't pack non-peripheral register <name> to I/O pin <name> -- too few peripheral buses

Can't pack non-peripheral register <name> to I/O pin <name> -- too few peripheral buses

Can't pack non-peripheral register <name> to I/O pin <name> -- too few peripheral buses

Can't pack non-peripheral register <name> to input pin <name> -- combinatorial logic between input pin and register

Can't pack non-peripheral register <name> to input pin <name> -- combinatorial logic between input pin and register

Can't pack non-peripheral register <name> to input pin <name> -- combinatorial logic between input pin and register

Can't pack non-peripheral register <name> to input pin <name> -- not enough I/O pins in the device

Can't pack non-peripheral register <name> to input pin <name> -- the pin has been assigned to a dedicated clock pin

Can't pack non-peripheral register <name> to output pin <name> -- register does not drive pin directly

Can't pack non-peripheral register <name> to output pin <name> -- register does not drive pin directly

Can't pack non-peripheral register <name> to output pin <name> -- register does not drive pin directly

Can't pack non-peripheral register <name> to output pin <name> -- register drives global bus

Can't pack non-peripheral register <name> to output pin <name> -- register drives global bus

Can't pack non-peripheral register <name> to output pin <name> -- register drives global bus

Can't pack non-peripheral register <name> to output pin <name> -- register drives peripheral bus

Can't pack non-peripheral register to I/O pin <name> -- pin cannot have more than one fan-out

Can't pack RAM ADDRESS_WIDTH <number> and DATA_WIDTH <number> to location <number>

Can't pack register <name> as an output register to fast I/O pin <name> because register feeds back to the core

Can't pack register <name> to fast I/O pin <name> as an output register because it feeds back to the core

Can't pack two nodes in one logic cell because they are both either registers or combinatorial cells

Can't parse Routing Constraints File line <number> -- a route port cannot be specified unless the atom is an LE

Can't parse Routing Constraints File line <number> -- atom <name> does not exist

Can't parse Routing Constraints File line <number> -- route port <name> is not valid

Can't parse Routing Constraints File line <number> -- The atom <name> and port <name> are not a target on signal <name>

Can't parse Routing Constraints File line <number> because either the input port <name> or the bus index <number> is not valid for atom <name>

Can't parse Routing Constraints File line <number> because label <name> does not exist

Can't parse Routing Constraints File line <number> because maf name <name> does not exist

Can't parse Routing Constraints File on line <number> -- string <name> is not valid

Can't paste to clipboard contents to read-only memory cells

Can't perform <name> register packing because of user assignments for nodes in some register-node combinations

Can't perform fitting netlist optimizations during fast fit compilation

Can't perform functional simulation of Excalibur component <name>

Can't perform HardCopy performance estimation on design before timing analysis -- run timing analysis on design

Can't perform HardCopy performance estimation on design with target device <name>

Can't perform hierarchical synthesis on <name> entity due to bidirectional connections between hierarchies

Can't perform hierarchical synthesis on <name> entity due to netlist optimizations using Fitter timing information

Can't perform hierarchical synthesis on <name> entity due to tri-state connections between hierarchies

Can't perform incremental compilation for preferred locations because node <name> of type <type> is not assigned to a specific location

Can't perform incremental compilation for preferred locations because of unplaced or illegally placed carry or cascade chain

Can't perform multiclock timing analysis -- specify clock frequency requirements

Can't perform netlist optimizations during SignalProbe compilation

Can't perform netlist optimizations when timing-driven compilation is turned off

Can't perform resynthesis -- TCL Script File needed to generate contraints files does not exist

Can't perform SignalProbe compilation -- SignalProbe information not saved during previous smart compilation

Can't perform SignalProbe compilation -- SignalProbe information not saved during previous smart compilation

Can't perform SignalProbe compilation -- SignalProbe information corrupted in Compiler database

Can't perform SignalProbe compilation -- SignalProbe information corrupted in Compiler database

Can't perform SignalProbe compilation because the design requires a full compilation. To perform a SignalProbe compilation, recompile the design.

Can't perform software build because no software source files are specified for project

Can't place <bidirectional pin or output pin> <name> in <fast input pin> <name>

Can't place <embedded cell, product term, or CAM> <name> because both clock and clear are non-global

Can't place <labs> LABs in the union of <number> overlapping custom regions because only <number> LABs can fit in the region

Can't place <name> block because target device does not support block <name>

Can't place <name> pin <name> in dedicated location (<number>, <number>, <number>)

Can't place <name> pin <name> in location (<number>, <number>, <number>)

Can't place <name> pin to HSDI receiver pin location

Can't place <number> <type> in region <name> because the region can contain only <number> <type>

Can't place <number> entities or nodes in location <name> because location <name> cannot contain more than <number> entities or nodes

Can't place <number> entities or nodes of type <type> in location <name> because location <name> cannot contain more than <number> entities or nodes

Can't place <number> I/O cells of type <type> in location <name> because location <name> cannot contain more than <number> I/O cells

Can't place <number> I/O pins in region <name> because the specified region cannot contain more than <number> I/O pins

Can't place <number> LABs from <number> logic cells in the region <name> because only <number> LABs can fit in the region

Can't place <number> LABs in the intersection of <number> overlapping regions because only <number> LABs can fit in the region

Can't place <number> logic cells in clique <name> of type <type> because clique <name> cannot contain more than <number> logic cells

Can't place <number> logic cells of type <type> in clique <name> of type <type> because clique <name> cannot contain more than <number> logic cells

Can't place <number> macrocells in LAB <name> because the LAB cannot contain more than <number> macrocells

Can't place <number> nodes or entities in lab clique <name> because clique can contain only <number> nodes or entities

Can't place <number> nodes or entities in region <name> because the region cannot contain more than <number> nodes or entities

Can't place <number> nodes or entities of type <type> in clique <name> because clique can contain only <number> nodes or entities

Can't place <number> nodes or entities of type <type> in clique <name> of type <type> because the clique can contain only <number> nodes or entities

Can't place <number> nodes or entities, which must be placed in LE1 of a LAB, in clique <name> of type <type> because the clique can contain only <number> nodes or entities

Can't place <number> output pins that are driven by macrocells in lab clique <name> because clique can contain only <number> output pins

Can't place <number> pins in LAB <name> because the LAB cannot contain more than <number> pins

Can't place <number> RAM blocks or portions of RAM blocks in design

Can't place <number> sharable expanders in LAB <name> because the LAB can contain only <number> sharable expanders

Can't place <number> shareable expanders in lab clique <name> because clique can contain only <number> shareable expanders

Can't place <number> signals of type <type> in clique <name> of type <type> because clique <name> cannot contain more than <number> signals

Can't place <number> signals of types <type> and <type> in clique <name> of type <type> because clique <name> cannot contain more than <number> signals

Can't place <number> signals of types <type>, <type>, <type>, and <type> in clique <name> of type <type> because clique <name> cannot contain more than <number> signals

Can't place <type> <name>

Can't place <type> <name> in region <name>

Can't place <type> slice <name>, which contains <number> nodes

Can't place all I/O pins in the current design

Can't place both node <name> and node <name> in location <name>

Can't place both node <name> and node <name> in region <name>

Can't place both node <name> and node <name> in region <name>

Can't place carry chain of chain length <number> that starts with logic cell <number> because it is too long for current device, which can contain chain no longer than of chain length <number>

Can't place carry chain of chain length <number> that starts with logic cell <number> because it is too long for the current device, which can contain a chain no longer than chain length <number>

Can't place carry chain of chain length <number> that starts with logic cell <number> because it is too long for the current device, which can contain a chain no longer than of chain length <number>

Can't place carry chain of chain length <number> that starts with logic cell <number> because it requires <number> signals of type <type>, <type>, <type>, <type>, and <type>, but device can contain only <number> signals

Can't place carry chain of chain length <number> that starts with logic cell <number> because it requires <number> signals of type <type>, <type>, and <type>, but device can contain only <number> signals

Can't place carry chain of chain length <number> that starts with logic cell <number> because it requires <number> signals of type <type>, <type>, and <type>, but the device can contain only <number> signals

Can't place carry chain of chain length <number> that starts with logic cell <number> because it requires <number> signals of type <type>, but device can contain only <number> signals

Can't place carry chain of chain length <number> that starts with logic cell <number> because it requires <number> signals of type <type>, but the device can contain only <number> signals

Can't place carry chain of chain length <number> that starts with logic cell <number> because it requires <number> signals of types <type>, <type>, <type>, <type>, and <type>, but the device can contain only <number> signals

Can't place carry chain of chain length <number> that starts with logic cell <number> because its member cells do not all use signal type <type>, which is enabled for entire LAB

Can't place carry chain of chain length <number> that starts with logic cell <number> because its member cells do not all use signal type <type>, which is enabled for the entire LAB

Can't place carry chain that starts with node <name>

Can't place carry chain that starts with node <name> -- carry chain uses multiple S_LOAD signals

Can't place carry or cascade chain of chain length <number> that starts with logic cell <number> because it is too long for current device, which can contain chain no longer than of chain length <number>

Can't place carry or cascade chain spanning <number> logic cells and starting on logic cell <name>

Can't place carry or cascade chain starting with cell <name>

Can't place carry or cascade chain that starts with logic cell <name> due to secondary signal requirements

Can't place carry or cascade chain, spanning <number> logic cells and starting on logic cell <name>, inside LogicLock region <name>

Can't place CARRY primitive <name> -- logic cell requires more inputs than it can contain

Can't place cascade chain that starts with node <name> because of conflicting assignments

Can't place cascade chain that starts with node <name> in location <name> because of conflicting assignments

Can't place cell <name> of type <type> in LAB clique <type> because the cell is not a logic cell

Can't place cell <name> of type <type> in LAB clique <type> because the cell is not a logic cell

Can't place clique <name> because clique contains member nodes with conflicting location assignments

Can't place clique <name> containing <number> logic cells

Can't place clique <name> in LAB because logic cells of clique do not all use signal <type>, which is enabled for entire LAB

Can't place clique <name> in LAB because the logic cells of the clique do not all use signal <type>, which is enabled for the entire LAB

Can't place clique <name> of type <type> because it is not supported

Can't place clique <name> of type <type> because it is not supported

Can't place clock input node <name> in location <name> because location cannot support clock input frequency higher than <number> MHz

Can't place clock signal <name> due to conflicting location requirements or incompatible I/O standards

Can't place ClockLock PLL <name>

Can't place ClockLock PLL <name> because of device I/O pin assignments

Can't place ClockLock PLL <name> because of the assignments made to its corresponding I/O pins

Can't place ClockLock PLL <name> because of user I/O pin assignments

Can't place ClockLock PLL <name> in ClockLock PLL_<number> circuitry because another ClockLock PLL in the design is already using the global signal required by the <type> port

Can't place ClockLock PLL <name> in ClockLock PLL_<number> circuitry because another ClockLock PLL in the design is already using the global signal required the <type> port

Can't place ClockLock PLL <name> in ClockLock PLL_<number> circuitry because another node is assigned to ClockLock PLL circuitry's <type> pin (<name>)

Can't place ClockLock PLL <name> in ClockLock PLL_<number> circuitry because another node is assigned to pin <name>, which feeds the same global signal as this ClockLock PLL circuitry's port of type <type>

Can't place ClockLock PLL <name> in ClockLock PLL_<number> circuitry because node <name>, which feeds port of type <type>, also feeds to other destinations, but the global signal required to feed to these destinations is already occupied

Can't place ClockLock PLL <name> in ClockLock PLL_<number> circuitry because node of type <type> cannot be assigned to this ClockLock PLL circuitry's <type> pin

Can't place ClockLock PLL <name> in ClockLock PLL_<number> circuitry because pin <type>, to which you made assignment, does not feed this circuitry

Can't place ClockLock PLL <name> in ClockLock PLL_<number> circuitry because pin <type>, to which you made assignment, is not fed by this circuitry

Can't place ClockLock PLL <name> in ClockLock PLL_<number> circuitry because this ClockLock PLL circuitry's <type> pin is already being used by another ClockLock PLL in the design

Can't place ClockLock PLL <name> in migration device because of device migration constraints

Can't place ClockLock PLL <name> in PLL location <name> -- ClockLock PLL or one of its I/Os is assigned to opposite horizontal half of device as the PLL location

Can't place ClockLock PLL <name> in PLL location <name> -- ClockLock PLL output port of type <name> cannot access global interconnect from PLL location <name>

Can't place ClockLock PLL <name> in PLL location <name> -- ClockLock PLL output port of type <name> cannot feed LVDS Transmitter PLL when placed in PLL location <name>

Can't place ClockLock PLL <name> in PLL location <name> -- Fitter can't place I/O node <name>, which is connected to ClockLock PLL port of type <name>

Can't place ClockLock PLL <name> in PLL location <name> -- global interconnect needed by ClockLock PLL output port of type <name> is already used by node <name>

Can't place ClockLock PLL <name> in PLL location <name> because the location does not allow a clock enable port

Can't place ClockLock PLL <name> in PLL location <name> because the location does not allow a clockout port

Can't place ClockLock PLL <name> in PLL location <name> because the location does not allow a feedback in port

Can't place ClockLock PLL <name> in PLL location <name> because the location does not allow a locked output port

Can't place ClockLock PLL <name> in PLL location <name> because the location is already occupied by node <name>

Can't place ClockLock PLL <name> in selected device due to device constraints

Can't place ClockLock PLL <name> in the selected device

Can't place ClockLock PLL <name> in the selected device due to hardware constraints

Can't place ClockLock PLL <name> in the selected device due to hardware constraints

Can't place CRC block <name> in dedicated location (<number>, <number>, <number>)

Can't place custom region <name> -- region exceeds the boundaries of the target device or is assigned to an illegal location

Can't place custom region -- region exceeds the boundaries of the target device

Can't place DDR pin group that is driven by DQS I/O pin <name> because DQS I/O pin can't be placed in DQS I/O pin location <name> in device

Can't place differential I/O pins and/or associated SERDES transmitters or receivers due to illegal location assignments

Can't place DQ I/O pin <name> due to resource assignments

Can't place DQ I/O pin <name> in DQ I/O pin location associated with DQS I/O pin <name> in device

Can't place DQS I/O pin <name> and its associated DQ I/O pins in designated DQS I/O pin <name> in device because its associated DQ I/O pins cannot be placed in designated DQ I/O pins in device

Can't place DQS I/O pin <name> and its associated DQ I/O pins in designated DQS I/O pin location <name> with associated DQ I/O pins in device because custom region assignments in design do not include logic elements that feed DQ and DQS I/O pins

Can't place DQS I/O pin <name> because its assigned location does not include any designated DQS I/O pins in device

Can't place enhanced PLL <name> because its inclk0 pin <name> is assigned to I/O location (<name>) that can feed only inclk1 port of PLL

Can't place enhanced PLL <name> because its inclk1 pin <name> is assigned to I/O location (<name>) that can feed only inclk0 port of PLL

Can't place enhanced PLL <name> in PLL location <name> because location does not accept enhanced PLLs

Can't place enhanced PLL <name> in PLL location <name> because PLL has different parameters for C0 and E0 counters

Can't place enhanced PLL <name> in PLL location <name> because the location does not allow a feedback in port

Can't place fast input register for node <name> because the device doesn't support fast input register

Can't place fast or enhanced PLL <name> because it is assigned to incompatible location

Can't place fast or enhanced PLL <name> because one of its I/O pins <name> has an incompatible location assignment

Can't place fast or enhanced PLL <name> in PLL location <name> because I/O cell <name> (port of type <type> of the PLL) has an incompatible location assignment with PLL I/O pin <name>

Can't place fast or enhanced PLL <name> in PLL location <name> because I/O cell <name> (port type <type> of the PLL) is placed in an incompatible I/O pin <name>

Can't place fast or enhanced PLL <name> in PLL location <name> because its input clock <name> has a frequency higher than PLL I/O pin <name> can support

Can't place fast or enhanced PLL <name> in PLL location <name> because location does not accept a non-I/O input clock <name>

Can't place fast or enhanced PLL <name> in PLL location <name> because location is already occupied by node <name>

Can't place fast or enhanced PLL <name> in PLL location <name> because PLL has a location assignment incompatible with the PLL location in the device

Can't place fast or enhanced PLL <name> in PLL location <name> because PLL input clock port <name> requires too many routing resources of type <type>

Can't place fast or enhanced PLL <name> in PLL location <name> because PLL output clock port <name> requires too many routing resources of type <type>

Can't place fast or enhanced PLL <name> in PLL location <name> because PLL requires <number> external clock output ports but the PLL location only has <number> external clock output ports

Can't place fast or enhanced PLL <name> in PLL location <name> because the PLL I/O pin of port type <type> (<name>) is already occupied by node <name>

Can't place fast or enhanced PLL <name> in PLL location <name> because the PLL requires <number> clock output ports but the PLL location only has <number> clock output ports

Can't place fast or enhanced PLL <name> in PLL location <name> due to device constraints

Can't place fast or enhanced PLL <name> in target device due to device constraints

Can't place fast PLL <name> because it drives <number> differential <name> I/O nodes -- target device can support maximum of <number> differential I/O nodes per fast PLL

Can't place fast PLL <name> in PLL location <name> -- can't place clock input pin in legal location

Can't place fast PLL <name> in PLL location <name> -- location does not support dynamic phase alignment

Can't place fast PLL <name> in PLL location <name> because location does not accept fast PLLs

Can't place fast PLL <name> in PLL location <name> because no regional clock or global clock can be found for clock output port <name>

Can't place fast PLL <name> in PLL location <name> because PLL or one or more differential I/O nodes driven by it has incompatible location assignment

Can't place fast PLL <name> in PLL location <name> because too few differential I/O node locations available

Can't place fast PLL <name> with <number> Mbps data rate in PLL location <name>, which can support only <number> Mbps data rate

Can't place Flexible-LVDS I/O node <name> at dedicated LVDS I/O pin <name>

Can't place following RAM blocks or portions of RAM blocks -- design contains conflicting assignments

Can't place following RAM blocks or portions of RAM blocks -- design contains illegal assignments

Can't place GXB pin <name> at location <name> because of incompatible location or I/O standard assignments

Can't place GXB receiver channel <name>, a logical channel <number> in XAUI synchronization mode, at location <name>, a physical channel <number> in quad

Can't place GXB receiver channel <name>, a zero channel in XAUI synchronization mode, at location <name>

Can't place GXB transmitter or receiver channel <name> to location <name> due to conflicting location assignments

Can't place GXB transmitter or receiver channels and/or their associated I/O pins due to illegal location or I/O standard assignments or inappropriate device

Can't place GXB transmitter PLL <name> at location <name> due to conflicting location assignments

Can't place HSDI <name> and HSDI <name> fed by PLL <name> in I/O banks <number> and <number>

Can't place HSDI PLL <name>

Can't place HSDI PLL's clock input <name> because it must be assigned a global clock pin (clk1, clk2, or clk4) or the corresponding HSDI clock pin of the HSDI PLL

Can't place HSDI PLL's clock input <name> because it must be assigned to a global clock pin (clk1, clk2, or clk3) or or the corresponding HSDI clock pin of the HSDI PLL

Can't place HSDI receiver <name>

Can't place HSDI receiver <name> because of the assignments made to its corresponding I/O pins

Can't place HSDI receiver <name>, which has clock fan-out, in center receivers

Can't place HSDI receiver <name>, which has non-clock fan-outs, in selected device

Can't place HSDI receiver fan-out node <name>, which is fed by HSDI receiver node <name>, in associated LABs <name>

Can't place HSDI receiver's output node <name> because it has been assigned to illegal location

Can't place HSDI receivers and ClockLock PLLs because they require too many dedicated clock lines

Can't place HSDI transmitter <name>

Can't place HSDI transmitter <name> because of the assignments made to its corresponding I/O pins

Can't place HSDI transmitter <name> with data width 10 in channel <name>, which is near ELA pin

Can't place HSDI transmitter <name>, which has clock fan-out, in center receivers

Can't place HSDI transmitter fan-in node <name>, which feeds HSDI transmitter node <name>, in associated LABs <name>

Can't place HSDI transmitter's output node <name> because it has been assigned to illegal location

Can't place HSDI transmitters and ClockLock PLLs because they require too many dedicated clock lines

Can't place I/O node <name> in I/O bank <number> -- I/O bank <number> is full

Can't place I/O node <name> in I/O bank <number> -- I/O node <name> uses an LVDS I/O standard but I/O bank <number> does not support VCCIO voltage of 0 or 3.3V

Can't place I/O node <name> in I/O bank <number> -- I/O node and I/O bank use different VREF pins, but must use the same VREF pin

Can't place I/O node <name> in I/O pin <name> -- node already assigned to pin <name>

Can't place I/O node <name> in pin <name> -- pin is already occupied by node <name>

Can't place I/O pin <name> assigned with region (<number>, <number>) to (<number>, <number>) <text>

Can't place I/O pin <name> because it is assigned to a VREF location inside a HSDI I/O bank

Can't place I/O pin <name> in I/O bank <number> -- I/O bank is full

Can't place I/O pin <name> in non-bonded location <name>

Can't place I/O pin <name> in pin location <name> because I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available

Can't place I/O pin <name> in VREF pin location <name> because I/O standard assigned to pin requires VREF value

Can't place I/O pin <name> to location <name> because it already has incompatible custom region assignment (<number>, <number>) to (<number>, <number>) made by <name> source

Can't place illegal parallel expander chains of node <name> because the device doesn't support the parallel expander chain, or the length of parallel expander chain is longer than <number>

Can't place input clock <name> in I/O pin location <name> -- input clock <name> needs global interconnect to feed non-PLL destinations, but global interconnect is already used by node <name>

Can't place input clock <name> in I/O pin location <name> -- input clock <name> needs global interconnect to feed non-PLL destinations, but global interconnect is already used by output port of type <name> of ClockLock PLL <name>

Can't place input clock <name> in I/O pin location <name> -- input clock feeds multiple ClockLock PLLs

Can't place input LVDS I/O node <name> at output LVDS I/O pin <name>

Can't place input or bidirectional pin <name> in I/O bank <number> -- pin requires a VREF voltage of <name> but the I/O bank uses a VREF voltage of <name>

Can't place input pin <name> -- input pin <name> feeds clock enable port of ClockLock PLL <name>, but also feeds other logic

Can't place IO node <name> in pin <name> because the pin is too close to VREF pin

Can't place JTAG block <name> in location (<number>, <number>, <number>)

Can't place JTAG input pin <name> in location (<number>, <number>, <number>)

Can't place JTAG input pin <name> in location (<number>, <number>, <number>)

Can't place LAB clique <name> of type <type> -- ignored assignment

Can't place LAB of <number> logic cells

Can't place LAB of <number> logic cells constrained to region <name>

Can't place LAB of <number> logic cells constrained to region <name> -- <number> logic cells have a location assignment

Can't place location assignments for carry or cascade chain spanning <number> logic cells and starting on logic cell <name>

Can't place logic cells assigned to location <name>

Can't place logic cells assigned to one LAB into a single LAB

Can't place logic cells in LE1 in LAB <name> because LAB <name> is full

Can't place logic cells in LE1 in LAB clique <type> because LAB clique <type> is full

Can't place logic cells requiring <number> signals of type <type> in location <name> because location <name> cannot contain more than <number> signals

Can't place logic cells requiring <number> signals of types <type> and <type> in location <name> because location <name> cannot contain more than <number> signals

Can't place logic cells requiring <number> signals of types <type>, <type>, <type>, and <type> in location <name> because location <name> cannot contain more than <number> signals

Can't place logic cells that do not use <type> signal into <name>. In this device, <type> signals are global to the LAB; all or none of the logic cells must use it.

Can't place logic cells that do not use <type> signal type in LAB <name> because the LAB uses this type of signal, which is enabled for the entire LAB

Can't place logic cells that do not use the <type> signal into <name>. In this device, <type> signals are global to the LAB; all or none of the logic cells must use it.

Can't place logic cells that do not use the <type> signal into <name>. In this device, <type> signals are global to the LAB; all or none of the logic cells must use it.

Can't place logic fed by CARRY_SUM primitive <name> into a single logic cell

Can't place logic feeding CARRY_SUM primitive <name> in single logic cell

Can't place logic in LE1 in LAB

Can't place logic that uses <number> <type> in region <name> because the region can contain only <number> <type>

Can't place logic that uses <number> <type> in region <name> because the specified region can contain only <number> <type>

Can't place logic that uses <number> <type> in region <name> because the specified region contains only <number> <type>

Can't place LogicLock region <name>

Can't place LogicLock region <name>

Can't place LVDS I/O node <name> at non-LVDS I/O standard pin <name>

Can't place LVDS receiver <name>

Can't place LVDS receiver <name> because of assignments made to its I/O pins

Can't place LVDS receiver <name> in target device because of device migration constraints

Can't place LVDS receiver fan-out node <name> (which is fed by LVDS receiver node <name>) in MegaLAB <name> (which is next to the LVDS receiver) because of the assignment you made. As a result, LVDS performance may not meet your specifications.

Can't place LVDS transmitter <name>

Can't place LVDS transmitter <name> because of assignments made to its I/O pins

Can't place LVDS transmitter <name> in target device because of device migration constraints

Can't place LVDS transmitter fan-in node <name> (which feeds LVDS transmitter node <name>) in MegaLAB <name> (which is next to the LVDS transmitter) because of the assignment you made. As a result, LVDS performance may not meet your specifications.

Can't place macrocell <name> assigned to <name> and node <name> assigned to <name> -- Ignoring macrocell assignment

Can't place memory block <name> in any memory block type

Can't place memory block <name> in memory block type <type>

Can't place memory block type <type> in a location for memory block type <type>

Can't place memory block type <type> with operation mode <name> and mixed data widths of <number> bits for read port and <number> bits for write port

Can't place multi-LAB carry chain that starts with logic cell <name> of chain length <number> because it requires more secondary signals than device can contain

Can't place multiplier--node <name> has a location assignment to logic cell <name>

Can't place negative LVDS I/O node <name> at positive LVDS I/O pin <name>. Assign the I/O node to the negative LVDS I/O pin <name>.

Can't place node <name>

Can't place node <name>

Can't place node <name>

Can't place node <name>

Can't place node <name> -- illegal location assignment <name>

Can't place node <name> -- node has multiple location assignments on output ports

Can't place node <name> at back-annotated location <location> in LogicLock region <name>

Can't place node <name> constrained to location <name>, but without the location constraint the Fitter would have found a legal location for this node

Can't place node <name> in embedded cell <name> -- node is part of parallel expander chain that does not fit in the assigned Embedded System Block (ESB)

Can't place node <name> in location <name>

Can't place node <name> in location <name>

Can't place node <name> in location <name>

Can't place node <name> in location <name>

Can't place node <name> in location <name>

Can't place node <name> in location <name> because location already occupied by node <name>

Can't place node <name> in logic cell position <text> -- node is part of a carry or cascade chain that does not fit in the assigned MegaLAB structure

Can't place node <name> in pin <name> because the node is too far away from VREF pin

Can't place node <name> in pin <name> because VREF pin <name> has <number> VREF-dependent nodes with higher pin numbers next to it, but VREF pin <name> can support only <number> nodes with higher pin numbers next to it

Can't place node <name> in pin <name> because VREF pin <name> has <number> VREF-dependent nodes with lower pin numbers next to it, but VREF pin <name> can support only <number> nodes with lower pin numbers next to it

Can't place node <name> in PLL location <name> because node is not a ClockLock PLL

Can't place node <name> in region <name>

Can't place node <name> in region <name>

Can't place node <name> in region <name>

Can't place node <name> in region <name>

Can't place node <name> in region <name>

Can't place node <name> in region <name> -- node already assigned to region <name>

Can't place node <name> of type <type>

Can't place node <name> of type <type>

Can't place node <name> of type <type>

Can't place node <name> of type <type> to <name> of type <type>

Can't place node <name> of type <type> to <type> <name> because node is in input register mode

Can't place node <name> of type <type> to <type> <name> because node is in packed register mode

Can't place node <name> of type <type> to <type> <name> because node is in packed register mode with registered feedback

Can't place node <name> while propagating assignment to location <name> on node <name>

Can't place node <name> with location assignment <name> in LogicLock region <name>

Can't place node <name>, which feeds an HSDI PLL in the clock port, because the node's logic type is incorrect

Can't place node <name>, which feeds an HSDI PLL in the clock port, because the node's logic type is incorrect

Can't place node <name>, which feeds an HSDI PLL in the clock port, because the node's logic type is incorrect

Can't place node <name>, which is the first cell of a counter chain, in logic cell <name>

Can't place nodes or entities with product-term logic that do not have the Turbo Bit option enabled in Embedded System Block <name> because this option is enabled for the entire ESB

Can't place nodes or entities, which require <number> resources of type <type>, in region <name> because the region can contain only <number> resources

Can't place nodes or entities, which require <number> resources of type <type>, in region <name> because the region can contain only <number> resources

Can't place nodes or entities, which require <number> resources that must be placed in LE1 of a LAB, in region <name>, because the region can contain only <number> nodes or entities

Can't place output LVDS I/O node <name> at input LVDS I/O pin <name>

Can't place output or bidirectional pin <name> in I/O bank <number> -- pin requires a VCCIO of <name> and I/O bank uses a VCCIO of <name>

Can't place output or bidirectional pin <name> in input pin only location <name>

Can't place output pin <name> in I/O bank <number> -- pin is an open drain output and requires a VCCIO of 2.5V or 3.3V but the pin uses an I/O standard of 1.8V

Can't place output pin <name> in I/O bank <number> -- pin uses GTL I/O standard and cannot use a VCCIO of 1.8V

Can't place parallel expander chains assigned to LAB <name>

Can't place part or all <name> I/O pins driven by clock pin <name> -- not enough empty <name> I/O pins in device

Can't place part or all of DDR pin group driven by DQS I/O pin <name> -- device does not have enough available DQS or DQ I/O pins

Can't place PCI I/O pin <name> in I/O bank <number> -- pin uses a VREF voltage of <name> which cannot be supported by the I/O bank with VCCIO of <name>

Can't place pin <name> at assigned pin location <name> (<name>) because location is JTAG pin location

Can't place pin <name> at assigned pin location <name> (<name>) because that location is a dedicated PLL input pin location

Can't place pin <name> at assigned pin location <name> (<name>) because that location is dedicated clock input pin location

Can't place pin <name> at dedicated clock pin location because global clock not available and regional clock cannot be used due to location constraints of one or more destinations

Can't place pin <name> at dedicated clock pin location because I/O or LAB clock region limit exceeded for one or more destinations

Can't place pin <name> at location <name> (<name>) because that location is a dedicated programming pin location

Can't place pin <name> at location <name> (<name>) because that location is a dedicated VREF pin location

Can't place pin <name> at location <name> (<name>) because that location is a power pin location

Can't place pin <name> at location <name> (<name>) because that location is the negative input of a differential clock

Can't place pin <name> on dedicated clock pin

Can't place pin <name> on dedicated clock pin because no global or regional clock is available

Can't place pin <name> with differential I/O standard

Can't place pin <name> with I/O standard <name>, Termination setting <name>, and PCI I/O setting <name> due to device constraints

Can't place pin <name> with input register next to LVDS transmitter pin <name> in location <name>

Can't place pin <name> with input register next to LVDS transmitter pin <name> in location <name> for selected migration devices

Can't place pins -- DQS I/O pin <name> and the DQ pins that are driven by it are assigned to different groups of DQS and DQ I/O pins in the device

Can't place pins -- number of DQS I/O pins in design exceeds the number of available DQS and DQ I/O pins in device

Can't place pins assigned to pin location <name> (<name>)

Can't place pins due to device constraints

Can't place PLL <name> and HSDI <name> in I/O banks <number> and <number>

Can't place PLL enable pin <name>

Can't place port of type <type> of <type> <name> because another node was assigned to the specific <type> pin position

Can't place positive LVDS I/O node <name> at negative LVDS I/O pin <name>. Assign the I/O node to the correct positive LVDS I/O pin <name>.

Can't place RAM block <name> in assigned location - location out of memory

Can't place RAM block <name> in assigned location -- location cannot support more than two incompatible RAM assignments

Can't place RAM block <name> in assigned location -- location cannot support two incompatible RAM assignments

Can't place RAM block <name> in assigned location -- RAM too deep, too wide, or location does not support RAM features

Can't place receiver fast PLL <name> in PLL location <name> because its clock input pin cannot be placed at dedicated clock input pin of PLL in target device

Can't place remote update block <name> in dedicated location (<number>, <number>, <number>)

Can't place SERDES receiver or transmitter <name> with <number> Mbps data rate in location <name>, which can support only <number> Mbps data rate

Can't place system clock pin <name> driving DQS I/O pin(s)

Can't place the following nodes in a carry chain -- cannot find a common child LogicLock region

Can't place the following nodes in a cascade chain -- cannot find a common child LogicLock region

Can't place the following nodes in a DSP block slice -- cannot find a common child LogicLock region

Can't place the following nodes in region bounded by top left corner <location> and bottom right corner <location> because this region is already occupied by other nodes

Can't place VREF pin <name> in I/O bank <number> -- pin requires a VREF voltage of <name> but the I/O bank uses a VREF voltage of <name>

Can't place VREF-dependent node <name> in I/O bank, because I/O bank has no VREF pin assignment

Can't place XGMII state machine <name> at location <name> due to conflicting location assignments

Can't process ARM-based Excalibur embedded processor core on pin <name>

Can't process Auto SLD Node Entity section keyword <name>

Can't process state machine <name> using user-encoded method

Can't program <name> device with <name> Programmer Object File in current version of the Quartus II software

Can't program device <text> in JTAG mode--device will be bypassed in JTAG chain

Can't program EPC4, EPC8, or EPC16 configuration devices with HP-UX workstation

Can't program Jam Files and Jam Byte-Code Files containing device <text> while using In-Socket Programming mode

Can't promote cell <name> -- cell must be assigned to a dedicated input, dedicated fast input, or internal global location to drive global signals

Can't promote cell <name> -- cell must drive control signals to be a global signal

Can't promote cell <name> -- Fitter assigned cell to a location that is neither a dedicated input, dedicated fast input, nor internal global location

Can't promote clock signal <name> because it feeds GXB transmitter PLL or GXB receiver PLL that uses a predivider

Can't promote signal <name> to I/O cell signal of type <type>

Can't promote signal <name> to I/O cell signal of type <type>

Can't promote signal <name> to use any clock networks

Can't purge intermediate file <name>

Can't purge intermediate files when command-line command is specified to run during a software build

Can't put both content-addressable memory and product-term logic in Embedded System Block <name>

Can't put both content-addressable memory and RAM in Embedded System Block <name>

Can't put both RAM and product-term logic in Embedded System Block <name>

Can't read database directory <name>

Can't read database file <name>

Can't read format of location assignment <name> associated with assignment <name>

Can't read Memory Initialization File or Hexadecimal (Intel-Format) File <name> -- file cannot contain more than <number> memory words

Can't read Memory Initialization File or Hexadecimal (Intel-Format) File <name> -- setting all initial values to 0

Can't read Memory Initialization File or Hexadecimal (Intel-Format) File <name> -- setting all initial values to never match

Can't read memory words from Memory Initialization File or Hexadecimal (Intel-Format) File <name> -- file must contain at least one memory word

Can't read or find LMF file <name>

Can't read Slave Binary Image File <name>

Can't recognize <name> <signal or parameter> for <PLL type or PLL mode> PLL <name>

Can't recognize <name> value for <name> parameter in PLL <name>

Can't recognize current focus entity

Can't recognize device <name>

Can't recognize device or device family

Can't recognize exit code <number> for Jam Byte-Code File <name>

Can't recognize node <name> in vector source file -- ignoring node when writing test bench files

Can't recognize pin number <number> as legal pin number -- choose a different pin

Can't recognize silicon ID for device <number>

Can't recognize the specified device family <name>

Can't recognize value <name> for EXTCLK0_COUNTER parameter in PLL <name> because SCAN_CHAN parameter is set to SHORT -- EXTCLK0_COUNTER parameter must be set to G0

Can't recognize value <text> as legal <location> element of a custom region assignment -- choose a different location

Can't recognize value <text> as legal <location> element of a location assignment -- choose a different location

Can't recognize value <text> as legal integer -- reverting to original assignment value

Can't recognize value <text> as legal location - reverting to original assignment value

Can't recognize value for <name> parameter for WYSIWYG RAM primitive <name>

Can't recognize value for <name> parameter for WYSIWYG RAM primitive <name>

Can't recover from node type mismatch

Can't remove assignment -- can't find assignment

Can't remove global option <name> because it is not defined in Slave Binary Image File

Can't remove global option <name> from Slave Binary Image File

Can't remove incompatible database file <name> from database directory

Can't remove incompatible database files from project

Can't remove peripheral <name> from register base address <text> in Slave Binary Image File

Can't remove VHDL or Verilog HDL Design File

Can't rename LogicLock region <name> -- a LogicLock region named <name> already exists in the project

Can't rename LogicLock region <name> -- a LogicLock region named <name> already exists in the project

Can't rename LogicLock region <name> -- type a new name

Can't rename LogicLock region <name> -- type a new name

Can't replace memory cell contents

Can't replace one or more memory cells

Can't replace with empty string

Can't reserve all unused logic cells in LogicLock region <name> -- placed the following additional nodes inside the boundaries of this region

Can't reserve configuration pin RDYnBSY -- not supported in target device

Can't reserve configuration pins DATA[7..1] -- not supported in target device

Can't reserve configuration pins nWS, nRS, nCS, and CS -- not supported in target device

Can't reserve pin <name> because it has an illegal I/O standard assignment

Can't reserve pin <name> because it has no I/O standard assignment

Can't reserve pin <name> because it lacks a legal location assignment

Can't reserve pin <name> because it lacks a location assignment

Can't reserve pin <name> because it lacks a location assignment

Can't reserve pin <name> because it lacks a location assignment

Can't reserve pin <name> because that name already exists

Can't reserve pin <name> because that name already exists

Can't reserve pin <name> because that name already exists

Can't reserve pin <name>: <text>

Can't resolve arithmetic expression because nesting is too deep

Can't route clock or clear signal to user assigned I/O cell <name> -- too many peripheral clock or clear signals required

Can't route clock or clear signal to user assigned peripheral I/O pin <name> -- too many peripheral clock or clear signals

Can't route LVDS transmitter <name> to LVDS output node <name> because they have conflicting assignments

Can't route signal <name> to atom <name>

Can't route source node <name> of type <type> to destination node <name> of type <type>

Can't route source node <name> of type <type> to destination node <name> of type <type>

Can't route source node <name> of type <type> to destination node <name> of type <type>

Can't route source node <name> of type <type> to destination node <name> of type <type>

Can't route source node <name> of type <type> to destination node <name> of type <type>

Can't route source node <name> of type <type> to the <port type> port of destination node <name> of type <type>

Can't route to GPI port of ARM-based Excalibur embedded processor stripe -- dual-port RAM input data routing options are swapped

Can't run command-line command after software build because command-line command is not specified

Can't run command-line command during software build because command-line command is not specified

Can't run Design Assistant -- Design Assistant does not support target device

Can't run Quartus II Help because required runtime patches are missing or environmental variables required to run Help are already set

Can't run SignalTap II -- download a design with the current SRAM Object File

Can't run SignalTap II -- SignalTap II File is not compatible with the file programmed in the device

Can't run SignalTap II -- specify communications cable and device

Can't run SignalTap II Logic Analyzer -- SignalTap II File is not compatible with the file programmed in the device

Can't run simulation tool -- compile project successfully before running simulation tool

Can't run Tcl command <text> specified in Tcl toolbar button number <number>

Can't run Tcl command with Tcl toolbar button number <number> -- no command specified

Can't run Tcl Script File <name>

Can't satisfy both Fast Output Register and Fast Input Register assignments on bidir pin <name>. Only one assignment can be satisfied.

Can't save assignment -- assignment already exists

Can't save assignment -- illegal assignment for settings and configuration file section

Can't save Chain Description File <name> -- device list contains unknown or undetermined device(s)

Can't save Chain Description File <name> because programming file <name> has not been saved

Can't save changes to Project Settings File

Can't save file <name>

Can't save incomplete assignment -- missing field: <name>

Can't save incorrect assignment -- error: <text>

Can't save or open file <name>

Can't save or open file <name>

Can't scan device chain

Can't select a device because the settings are too restrictive: package = <name>, pin count = <name>, speed grade = <name>

Can't select a device from device family <name> because no devices in family are installed

Can't set breakpoint <name> on node type

Can't set LPM_SHOWAHEAD parameter to ON for a FIFO buffer in Stratix devices

Can't set LPM_SHOWAHEAD parameter to ON for a FIFO buffer in Stratix devices

Can't set size of LogicLock region <name> to auto -- target device is from the Mercury device family

Can't set size of LogicLock region <name> to Auto because region has child LogicLock regions with locked locations

Can't set state of LogicLock region <name> to floating -- target device is from the Mercury device family

Can't simulate design -- Simulator Settings File <name> is missing or contains errors

Can't specify a device for device migration and view the last compiled result in the Last Comilation Floorplan-- recompile the design and reopen the Last Compilation floorplan

Can't split carry or cascade chain crossing <number> logic cells and starting on logic cell <name> into legal LABs

Can't start <Compiler, Simulator, Database Builder, or Software Builder> process

Can't start <name> while Quartus II software is running a process or is in batch mode

Can't start device configuration because no programming options have been selected for device chain

Can't start external text editor. Do you want to use default Quartus II Text Editor?

Can't start placement of multiplier in <type> <name> because logic cell <name> must have a Rapid LAB Interconnect connection to another logic cell to place node <name>

Can't start placement of multiplier in <type> <name> because node <name> must be placed in logic cell <name>

Can't start placement of multiplier in <type> <name> because the cin port of logic cell <name> must be fed by another logic cell to properly place node <name>

Can't start placement of multiplier in <type> <name> because the cout port of logic cell <name> must feed another logic cell to properly place node <name>

Can't start placement of multiplier in <type> <name> because the dataa port of logic cell <name> must be fed by a RapidLAB interconnect connection from another logic cell to properly place node <name>

Can't start placement of multiplier in <type> <name> because the datab port of logic cell <name> must be fed by a Rapid LAB Interconnect connection from another logic cell to properly place node <name>

Can't start server <name>. Beginning attempt <number> of <number> attempts to start server.

Can't stop the <Compiler, Simulator, or Database Builder> -- process already canceled due to internal error

Can't successfully place I/O cells

Can't support both Increase Delay to Output Enable Pin and Increase tzx Delay to Output Pin logic options on node <node name>

Can't support designs containing deep RAM -- contact Altera Customer Applications

Can't support remote update difference file with file extension <name>

Can't turn on Reserve unused logic cells for LogicLock region <name> because region is soft

Can't turn on Soft for LogicLock region <name> because region has Reserve unused logic cells turned on

Can't update Block Design File because Block Symbol File for block(s) cannot be found -- save current BDF before updating

Can't update Block Design File because Block Symbol File for symbol(s) cannot be found -- save current BDF before updating

Can't update database file <name>

Can't update JTAG Server with selected hardware: <type>

Can't update remote update block update register at time <time> -- update register in Application Configuration mode

Can't use <clk1> port of <LVDS receiver PLL> <name>

Can't use active serial memory interface block -- configuration scheme is not Active Serial

Can't use assignment <assignment type> for cell <cell name>

Can't use conduits in network without blocks

Can't use configuration device <name> with selected programming mode

Can't use Fast Row Interconnect logic option between I/O cell <name> and node <name> because the destination node cannot support all Fast Row Interconnect assignments that drive it

Can't use Jam Files with remote JTAG server

Can't use JTAG port <name> in current design

Can't use minimal number of bits to encode state machine <name>

Can't use post-fitting node <name> as a clock signal

Can't use programming file <name> because it contains an unsupported file extension

Can't use software toolset <name> with embedded processor core <name>

Can't use the node <name> as a Trigger Out signal

Can't use the post-fitting node <name> as a Trigger In signal

Can't validate assignment in settings and configuration file <name>

Can't verify device

Can't verify device <number>

Can't write Excalibur embedded processor stripe as a single module or entity because dual-port RAMs not placed

Can't write to database directory <name>

Can't write to database directory <name>

Can't write to database file <name>

Can't write to database file <name>

Can't write to database file <name>. Database error: <text>

Can't write to database file <name>. Database error: <text>

Can't write to file <name>

Can't write to port B of memory block <name> at time <time> -- port A is already writing to at least one or more bits of port B.

Can't write to settings and configuration file <name>

Can't write to settings and configuration file <name>

Can't write to Slave Binary Image File <name>

Can't write VQM File -- compile project successfully before generating output files

Canceled analysis of design entity <name> -- number of errors in Text Design File for entity cannot exceed maximum of <number>

Cannot find clock setting on system clock <text> for DQS pin <text>.

Cannot perform fast fit compilation because fast fit compilation is not supported for the selected device family

Cannot reserve SignalProbe output pin <name> as the location assignment to <name> is invalid. The assignment will be ignored.

Can’t place GXB clock input pin <name> because it drives a PLL that is not a GXB transmitter PLL or fast PLL -- pin must be placed inside quad because of I/O standard or location assignments

Carry chain containing following nodes spans multiple related LogicLock regions -- moved all nodes on chain into region <name>

Carry chain or cascade chain spans LogicLock regions <name> and <name>

Carry chain or cascade chain starting on node <name> spans multiple LogicLock regions

Carry chain spans multiple unrelated LogicLock regions

Carry chain that starts with CARRY primitive <name> requires <number> clear signals, but device can only contain <number> clear signals

Carry chain that starts with CARRY primitive <name> too long for the current device

Carry chain that starts with node <name> does not use invert A port

Carry chain that starts with node <name> uses invert A port

Carry or cascade chains cannot span multiple LogicLock regions -- moved the following nodes between regions

CARRY primitive <name> is part of cyclic carry chain

Cascade chain starts with node <name>

CASCADE primitive <name> contains fan-out to more than one destination

CASCADE primitive <name> fed by VCC or GND

CASCADE primitive <name> is fed by non-combinatorial logic

CASCADE primitive <name> is part of cyclic cascade chain

Cascin port of WYSIWYG LCELL primitive <name> is connected to gate primitive <name>, but must be connected to a WYSIWYG LCELL

Cascout port of WYSIWYG LCELL primitive <name> is connected to gate primitive <name>, but must be connected to a WYSIWYG LCELL

cbxi.lst file <name> contains one or more syntax errors

CDB: node or entity assigned to pin <name>, but this pin is beyond device boundary

Cell <name>, which is mapped to cell <name>, is missing the following Library Mapping File port mapping(s) for instance <name>

Cells placed in cell region <name> require <number> signals of types <type> and <type>, but the specified cell region can only contain <number> signals

Cells placed in LAB <name> require <number> inputs but the LAB can only contain <number> inputs

Changed compensation clock parameter for PLL <name> to regional clock instead of global clock setting because PLL is placed in location that compensates for regional clock only

Changed default I/O standard <text> to I/O standard <text> for HSDI transmitter or receiver input or output pin <name>

Changed LogicLock region assignment of node <name> from LogicLock region <name> to LogicLock region <name>

Changed LogicLock region assignments on the following nodes

Changed operation mode of PLL <name> to <name>

Changed operation mode of WYSIWYG I/O primitive <name> from type <type> to type <type> to match type of pin <name> connected to its padio port

Changed operation mode of WYSIWYG I/O primitives to match their padio pin type

Changing lock parameter of ClockLock PLL <name> from <number> to <number> input clock half cycles

Changing lock parameter of PLL <name> from <number> to <number> half clock cycles of the pre-scaler output

Changing the configuration device or programming file type will remove all files from the Input files to convert list. Do you want to continue?

Changing unlock parameter of ClockLock PLL <name> from <number> to <number> input clock half cycles

Changing unlock parameter of PLL <name> from <number> to <number> half clock cycles of the pre-scaler output

Checksum on line <number> does not match expected checksum

cin and regcascin ports of LCELL atom <name> have different sources

cin port of HSDI PLL ATOM <name> must be driven by I/O pin or HSDI receiver

cin port of HSDI receiver PLL ATOM <name> must be driven by I/O pin

Cin port of WYSIWYG LCELL primitive <name> connected to gate primitive <name>, but must be connected to a WYSIWYG LCELL

Circuit may not operate. <number> non-operational path(s) clocked by clock <name> have clock skew larger than the data delay. See the Compilation Report for details.

Clique <name> of type <type> requires <number> signals of type <type>, <type>, <type>, <type>, and <type>, but the clique can contain only <number> signals

Clique <name> of type <type> requires <number> resources of type <type>, but the clique can contain only <number> resources

Clique <name> of type <type> requires <number> signals of type <type> and <type>, but the clique can contain only <number> signals

Clique <name> of type <type> requires <number> signals of type <type> and <type>, but the specified region can contain only <number> signals

Clique <name> of type <type> requires <number> signals of type <type>, <type>, and <type>, but the clique can contain only <number> signals

Clique <name> of type <type> requires <number> signals of type <type>, but the clique can contain only <number> signals

Clique <name> of type <type> requires <number> signals of type <type>, but the clique can contain only <number> signals

Clique name: <name>

clk port of ClockLock PLL, LVDS receiver PLL, or LVDS transmitter PLL <name> must be driven by non-inverted input pin or, in an LVDS transmitter PLL, the output of an LVDS receiver PLL

clk0 or clk1 output port of fast PLL <name> must drive only a clock input port of a SERDES receiver or transmitter

clk0 port of HSDI PLL ATOM <name> must drive only an HSDI receiver or transmitter

clk0 port of WYSIWYG primitive <name> cannot be specified if it is not used

clk0 port of WYSIWYG primitive <name> cannot be specified if it is not used

clk1 port of HSDI PLL ATOM <name> drives logic other than a simple output pin

clk1 port of HSDI PLL ATOM <name> drives too many output pins

clk1 port of LVDS transmitter PLL <name> can fan out only to one output pin

clk1 port of WYSIWYG primitive <name> cannot be specified if it is not used

clk1 port of WYSIWYG primitive <name> cannot be specified if it is not used

CLK3 or CLK4 pin use is illegal -- these pins cannot drive other logic in APEX 20KE

CLKLK_ENA pin must be assigned LVTTL, LVCMOS, 1.8-V, or 2.5-V I/O standards

CLKLK_OUT pin cannot be assigned LVPECL I/O standard

CLKLOCK primitive <name> has illegal ClockBoost parameter value of <number>, but must be a value of 1 or 2

CLKLOCKx1 Input Frequency logic option can turned on for only input pins, but was turned on for non-input pin <name>

clkout output port of GXB receiver channel atom <name> must feed the coreclk input port of GXB receiver channel atom <name>

clkout pin of PLL <name> and dataout I/O pins of HSDI transmitters fed by PLL <name> may have inconsistent I/O standards because some of them have the <name> I/O standard assigned to them

CLKUSR option turned off for programming

Clock <name> <type> fmax is restricted to <number> between source <pin or register> <name> and destination <register or memory> <name>

Clock <name> frequency requirement of <number> overrides <name> PLL <name> input frequency requirement of <number>

Clock <name> frequency requirement of <number> should be in range between <number> and <number>. <name> PLL <name> input frequency requirement of <number> overrides clock <name> frequency requirement.

Clock <name> has <type> fmax of <number> between source <pin or register> <name> and destination <pin or register> <name> (period= <time>)

Clock enable ports must have same source when DDIO_MODE parameter is set to INPUT or OUTPUT for I/O ATOM <name>

Clock for register <name> fed by LVDS receiver <name> is not connected to the <name> port of LVDS receiver PLL

Clock frequency or clock divisor has illegal value

Clock input pin <name> drives fast PLL <name>, but also drives other logic -- must drive only fast PLL

clock input port must be connected when value of LPM_PIPELINE parameter is greater than 0

clock input port must be connected when value of LPM_PIPELINE parameter is greater than 0

clock input port must be disconnected when value of LPM_PIPELINE parameter is equal to 0

clock input port must be disconnected when value of LPM_PIPELINE parameter is equal to 0

Clock input port of fast PLL <name> must be driven by an I/O pin

Clock input port of HSDI PLL ATOM <name> should be driven by I/O pin

clock input port of the SERDES receiver or transmitter ATOM <name> is driven by an invalid port -- clock input port must be driven by a valid clock output port of a fast PLL

Clock multiplication of <number> and clock division of <number> are implemented for port <name>

Clock multiplication of <number> and clock division of <number> are implemented for port <name>

Clock period of <source or destination> clock <name> is <time> with <inverted or non-inverted> offset of <time> and duty cycle of <number>

Clock period specified in clock requirement for clock <name> must be greater than or equal to <time>

Clock pin <name> assigned to HSDI dedicated clock inputs must fan out only to HSDI PLL

Clock pin <name> feeding HSDI <transmitter or receiver> synchronizer must be assigned to a global clock pin

Clock pin <name>, which feeds to a HSDI receiver PLL that operates in LVDS mode, must be placed in HSDI clock pin HSDI_CLK2

clock port must always be connected

clock port must be connected when the LPM_PIPELINE parameter with value <integer> is greater than 0

clock port of atom <name> is disconnected or is connected to VCC or GND, but must be connected to legal clock pin or logic cell

clock port of atom <name> is disconnected or is connected to VCC or GND, but must be connected to legal clock pin or logic cell

clock port of atom <name> is disconnected or is connected to VCC or GND, but must be connected to legal clock pin or logic cell

Clock port of register <name> feeding LVDS transmitter <name> should not be inverted

Clock settings <name> already exists

Clock settings <name> cannot be assigned to input or output of PLL <name>

Clock settings <name> must have specified frequency

Clock settings <name> specifies duty cycle of <number>, but must specify duty cycle between 1 and 99

Clock signal <name> already exists

Clock signal <name> has estimated HardCopy fmax <number>

Clock signal in EPXA10 device cannot connect to RAM <name> in deep or wide RAM mode using local routing

Clock source error: illegal value <text> for <name> parameter

clock0 and clock1 input ports of LVDS transmitter <name> must be fed by the same LVDS transmitter PLL

clock0 and clock1 ports of <ClockLock PLL> <name> fan out to <number> output pins, but must not fan out to more than one output pin

Clock0 input of LVDS receiver <name> must be fed by clock0 port of the LVDS receiver PLL

Clock0 input of LVDS receiver <name> must be fed by LVDS receiver PLL clock0

Clock0 input of LVDS receiver <name> must be fed by LVDS receiver PLL clock0

Clock0 input of LVDS transmitter <name> must be fed by clock0 of the LVDS transmitter PLL

Clock0 input port of LVDS transmitter <name> must be fed by the LVDS transmitter PLL clock0

Clock0 input port of LVDS transmitter <name> must be fed by the LVDS transmitter PLL clock0

clock0 output port of GXB transmitter PLL <name> must connect only to fastpllclk port of GXB transmitter channel atom

Clock1 input of LVDS receiver <name> must be fed by clock1 of LVDS receiver PLL

Clock1 input of LVDS receiver <name> must be fed by clock2 of LVDS receiver PLL

Clock1 input of LVDS receiver <name> must be fed by LVDS receiver PLL clock1

Clock1 input port of LVDS transmitter <name> must be fed by clock1 port of the LVDS transmitter PLL

Clock1 input port of LVDS transmitter <name> must be fed by clock2 port of the LVDS transmitter PLL

Clock1 input port of LVDS transmitter <name> must be fed by the LVDS transmitter PLL clock1

Clock1 input port of LVDS transmitter <name> must be fed by the LVDS transmitter PLL clock1

Clock1 input port of the LVDS receiver <name> must be fed by the LVDS receiver PLL clock1

clock1 output port of GXB transmitter PLL <name> must connect only to clock port of a GXB receiver channel atom, GXB transmitter channel atom, or XGMII state machine atom

clock1 port of <LVDS transmitter PLL> <name> fan out to <number> output pins, but must not fan out to more than one output pin

clock1 signals of synchronizer ATOM <name> and its HSDI <text> ATOM <name> are driven by different sources or same source but with different polarity.

Clocklock <name> requires a duty cycle of 50%, but clock <name> has a duty cycle of <number>

ClockLock feedback in port of ClockLock PLL <name> must not be connected when the ClockLock PLL is not in external feedback mode

ClockLock PLL <name> cannot feed logic -- can only feed the clock input of a DFF primitive or synchronous RAM megafunction in a positive polarity

ClockLock PLL <name> cannot have PHASE_SHIFT parameter value set to non-0 phase shift when OPERATION_MODE parameter value is set to something other than NORMAL. Forcing phase shift to 0.

ClockLock PLL <name> fans out to non-global destinations, but it can only feed globally -- automatically promoted to global

ClockLock PLL <name> has a connected ClockLock feedback in port, but the ClockLock external clock port must feed an output pin

ClockLock PLL <name> has an illegal CLK0_DIVIDE_BY or CLK1_DIVIDE_BY parameter value <number> for <name> output port

ClockLock PLL <name> has clock multiplication and clock division parameters that may cause jitter because loop multiplier value <number> is larger than <number>

ClockLock PLL <name> has illegal MULTIPLY_BY parameter value <number> for <name> output port

ClockLock PLL <name> has illegal or non-numeric value <text> for INPUT_FREQUENCY parameter

ClockLock PLL <name> has illegal parameter values

ClockLock PLL <name> has illegal value <number> for INVALID_LOCK_MULTIPLIER parameter

ClockLock PLL <name> has illegal value <number> for LOCK_HIGH parameter

ClockLock PLL <name> has illegal value <number> for LOCK_LOW parameter

ClockLock PLL <name> has illegal value <number> for VALID_LOCK_MULTIPLIER parameter

ClockLock PLL <name> has illegal value <text> for PHASE_SHIFT parameter

ClockLock PLL <name> has the <type> output port feeding node <name>, but the node must be an output pin

ClockLock PLL <name> input frequency requirement of <number> overrides clock <name> frequency requirement of <number>

ClockLock PLL <name> input frequency requirement of <number> overrides default required fmax of <number> -- Slack information will be reported

ClockLock PLL <name> is assigned to <location>

ClockLock PLL <name> lost lock on input signal at time <time> due to duty cycle violation

ClockLock PLL <name> lost lock on input signal at time <time> due to frequency violation

ClockLock PLL <name> lost lock on input signal at time <time> due to logic level violation

ClockLock PLL <name> must drive a clock port

ClockLock PLL <name> must drive a clock port

ClockLock PLL <name> must drive only a pin or clock port

ClockLock PLL <name> must feed an output pin when its OPERATION_MODE parameter is set to ZERO_DELAY_BUFFER

ClockLock PLL <name> must feed an output pin when OPERATION_MODE parameter is set to EXTERNAL_FEEDBACK

ClockLock PLL <name> must feed only one CLKLK_OUT pin

ClockLock PLL <name> must have a connected <type> port when in external feedback mode

ClockLock PLL <name> must have value for CLOCK1_BOOST or CLOCK2_BOOST parameter

ClockLock PLL <name> must have value for CLOCK1_BOOST or CLOCK2_BOOST parameter

ClockLock PLL <name> must have value for INPUT_FREQUENCY parameter

ClockLock PLL <name> must have value for INPUT_FREQUENCY parameter

ClockLock PLL <name> must have value for INPUT_FREQUENCY parameter

ClockLock PLL cannot have unsupported value for OPERATION_MODE parameter

ClockLock PLL cannot have unsupported value for OPERATION_MODE parameter

ClockLock PLL must contain input clock signal

ClockLock PLL must contain input clock signal

ClockLock PLL or WYSIWYG primitive <name> has illegal time delay parameter value <number> for output <name> port

ClockLock PLL parameter value <text> is not in range allowed for parameter

ClockLock PLL parameter value <text> is not in range allowed for value

ClockLock PLL PHASE_SHIFT parameter must be 0 when OPERATION_MODE parameter is not set to NORMAL

ClockLock PLL's PHASE_SHIFT parameter value cannot be set to non-0 phase shift when OPERATION_MODE parameter is not set to NORMAL

ClockLock PLL's PHASE_SHIFT parameter value cannot be set to non-0 phase shift when OPERATION_MODE parameter is not set to NORMAL

ClockLock PLL's PHASE_SHIFT parameter value set to inconsistent phase shifts between clk0 and clk1 ports

ClockLock PLLs <name> and <name>, both fed by input clock pin <name>, require <number> global clock lines but current device only allows <number>

clockout port of HSDI receiver <name> must drive a clock input port

clockout port of HSDI transmitter <name> must drive a clock input port

Clocks of a group of DQS I/O pins and their DQ I/O pins are driven by different PLLs

Closing Simulation Report window

clr0 port of WYSIWYG primitive <name> cannot be specified if it is not used

clr0 port of WYSIWYG primitive <name> cannot be specified if it is not used

clr1 port of WYSIWYG primitive <name> cannot be specified if it is not used

clr1 port of WYSIWYG primitive <name> cannot be specified if it is not used

cmp add_assignment <section_identifier> <source> <destination> <variable> <value>

cmp remove_assignment <section_identifier> <source> <destination> <variable> <value>

Column index of location <name> must be <name><number>

Combinatorial loop <number> contains <number> node(s)

Combinatorial output is <name>

Compared vector source file contains extra node <name>

Compared vector source file contains extra node <name>

Compared vector source file does not contain node <name>

Compensate clock of PLL <name> has been set to <name>

COMPENSATE_CLOCK parameter for PLL <name> has unsupported value <name> for <mode>

Compensating output pin <name>, which is fed by <name> port of enhanced PLL <name>

Compilation is in progress. Compiling design using previous Compiler settings -- changes made to Compiler settings since the compilation started will not take effect until you restart the Compiler.

Compilation is in progress. Compiling design using previous Compiler settings -- changes made to Compiler settings since the compilation started will not take effect until you restart the Compiler.

Compilation is in progress. Compiling design using previous Compiler settings -- changes made to Compiler settings since the compilation started will not take effect until you restart the Compiler.

Compilation is in progress. Compiling design using previous Compiler settings -- changes made to Compiler settings since the compilation started will not take effect until you restart the Compiler.

Compilation is in progress. Compiling design using previous Compiler settings -- changes made to Compiler settings since the compilation started will not take effect until you restart the Compiler.

Compilation is in progress. Compiling design using previous HardCopy settings -- changes made to HardCopy settings since the compilation started will not take effect until you restart the Compiler.

Compilation or simulation focus name <name> specified for <Compiler or Simulator> settings <name> contains illegal characters

Compilation Report contains advance information. Specifications for device <name> are subject to change. Contact Altera for information on availability. No programming file will be generated.

Compilation Report contains advanced information. Specifications for device <name> are subject to change. Contact Altera for information on availability. No programming file will be generated.

Compile the project to continue

Compiler inserted the following logic cells to protect hierarchy boundaries

Compiler Settings File <name> already exists for another project. If you do not select a different top-level design entity name for the project you are creating, you may lose data from the other project. Do you want to select a different top-level design entity name?

Compiler Settings File and Simulator Settings File <name> already exist for another project. If you do not select a different top-level design entity name for the project you are creating, you may lose data from the other project. Do you want to select a different top-level design entity name?

Compiler Settings File contains an illegal device <name> -- using default device instead

Compiler Settings File contains an illegal device family <name> -- using default device family <name>

Compiler Settings File contains an illegal device family <name> -- using default device family <name>

Compiler Settings File contains multiple Chip sections, but the Quartus II software does not support multidevice partitioning. Using chip <name>.

Compiler Settings File for <name> under project <name> cannot be found

Compiler settings name contains an illegal character -- specify a legal Compiler settings name

Compiler synthesized away node <name>. Ignored vector source file node.

Compiler warning: <text>

Compiling with the fast fit feature

Compiling with the fast fit feature

Completed encoding using <number> state bits

Condition expression defined in trigger <name> at level <number> contains a syntax error -- stopping processing at string <name>

CONF_DONE pin failed to go high

CONF_DONE pin failed to go high in device <number>

Configuration device <name> cannot be used with selected programming mode

Configuration device <name> cannot configure device <name>

Configuration device <name> cannot configure device <name>

Configuration device <name> data width cannot be greater than 1

Configuration device <name> does not support multiple pages

Configuration device <name> does not support remote or local update

Configuration device <name> does not support remote or local update

Configuration device <name> does not support remote or local update

Configuration failed

Configuration mode specified as Remote but remote update block is not found in design

Configuration pin DATA[0] is dedicated pin that does not need to be reserved

Configuration succeeded -- <number> device(s) configured

Configuring device index <number>

Conflict between multiple weak signals at time <time> on node <name>

Conflict between pull-up resistor and pull-down resistor for bidirectional pin

Conflicting vector exists for <input or output> node <name> at time <time> in vector source file <name> -- ignoring earlier vector

Connected node <name> to port <name>

Connection along critical path between <name> and <name>

Constant cannot be defined with quoted number or arithmetic expression <text>

Constant expression is unsupported

Constant expression specifies value longer than 32 bits -- truncated value

Constant or parameter <text> is used but not defined -- interpreted constant or parameter as quoted string

Content-addressable memory is set to single-match mode, but content-addressable memory contains multiple addresses with same data at time <time>

Content-addressable memory signal <name> is not stable during write cycle at time <time>

Content-addressable memory wrote an illegal value to bit 32 at time <time>. outputselect and wdatain must have same logic level if its MATCH_MODE parameter is set to MULTIPLE.

Conversion Setup File <name> is in an older Conversion Setup File format

Converted <number> DSP block slices

Converted <number> single input CARRY primitives to CARRY_SUM primitives

Converted bidirectional pin <name> to input pin

Converted bidirectional pin <name> to output pin

Converted presettable and clearable register to equivalent circuits with latches. Registers will power up to an undefined state, and DEVCLRn will place the registers in an undefined state.

Converted the following <number> DSP block slices to 18-bit multipliers

Converted the following <number> DSP block slices to logic elements

Converted the following <number> DSP block slices to Simple Multiplier mode

Converted TRI buffer to OR gate or removed OPNDRN

Converting MAX+PLUS II netlist arc to connector

Converting TRI node <name> that feeds logic to an OR gate

Core <name> is not enabled for current device family

Core clock signal of HSDI synchronizer ATOM <name> and its HSDI <text> ATOM <name> must be fed by logic

Core register <name> will power up low

Core register <name> will power up low

Core register <name> will power up low

coreclk input port frequency <number> of GXB transmitter channel atom <name> must be in the frequency range of <number> to <number>

coreclk input port of GXB receiver channel atom <name> is unconnected, but must be fed by either clock2 output port of a GXB transmitter PLL or clkout output port of GXB receiver channel atom <name>

coreclk input port of GXB receiver channel atom <name> must be fed by either clock2 output port of a GXB transmitter PLL or the clkout output port of GXB receiver channel atom <name>

Count Value is illegal for given radix

Cout port of WYSIWYG LCELL primitive <name> is connected to gate primitive <name>, but must be connected to a WYSIWYG LCELL

crcerror port of atom <name> drives <name>, which <name>, but crcerror port must drive non-registered output pin or bidirectional pin with VCC output enable signal

crcerror port of atom <name> has <number> fan-outs -- crcerror port must have only one fan-out

Create an instance

Created AHDL Include File <name>

Created Block Symbol File <name>

Created design file <name>

Created entity with duplicate name <name>

Created file in directory of your SignalTap II file: <SignalTap II Filename>.txt

Created LogicLock region <name>

Created manual logic duplication assignment <text> from source <text> and destination <text>

Created node <name> as a RAM by implementing register logic with Embedded System Block. Functionality differs from the original design.

Cross-Reference File <name> contains invalid text location syntax <text>

cruclk input frequency <name> of GXB receiver channel <name> does not equal output clock frequency <name> of source PLL

cruclk input port of GXB receiver channel atom <name> must be fed by pin or PLL

cruclk signal, cruclk period, and cruclk multiplier on GXB receiver channel <name> must be the same as used in other receiver channels in the same quad

Current adapter cannot be used with device <name>

Current density too high in I/O bank <number> -- these pins combined exceed the limit by <number>.<number> mA

Current design must use input port sload_data

Current design uses PLL enable input pin <name> and PLL enable input pin <name>, but only one PLL enable input pin can be used in <name> device family

Current device does not support Flexible-LVDS

Current device does not support HSDI

Current license file does not support device family <name> -- compilation support is not available

Current license file does not support the <name> device

Current license file does not support the <name> device family

Current migration devices not compatible with device selection -- select new migration devices?

Current power consumption limit exceeded for GNDIO group <name> -- electrical specifications may not be met

Current power consumption limit exceeded for GNDIO group <name> in migration device <name>-- electrical specifications may not be met

Current power consumption limit exceeded for VCCIO group <name> -- electrical specifications may not be met

Current power consumption limit exceeded for VCCIO group <name> in migration device <name> -- electrical specifications may not be met

Current process must be stopped before another project can be opened. Do you want to stop the current process?

Current programming hardware does not support <name> programming mode

Current simulation must be stopped before another project can be opened. Do you want to stop the current simulation?

Current software build must be stopped before another project can be opened. Do you want to stop the current software build?

Current Strength logic option is set to <text> for pin <name>, but setting is not supported by I/O standard <name>

Current Strength logic option setting for <name> node is illegal

Current Strength logic option setting for <name> node is illegal

Current trigger condition is not compatible with the last compilation result in instance <name>

Current vector source file <name> does not match compared vector source file <name>

Current vector source file <name> matches compared vector source file <name>

Current vector source file ends at time <time> and compared vector source file ends at time <time>

Custom or LogicLock region with top left corner of <location> and bottom right corner of <location>

Custom region for <name> I/O pin <name> must encompass <name> I/O pins on device

Custom regions on DQS I/O pin <name> and its DQ I/O pins do not merge to form a common region with DQS or DQ pins in device

D

Data file <name> must contain less than 65536 bytes of data

Data in passive programming files holds embedded processor core in reset because Hexadecimal (Intel-Format) Files do not contain initialization data for entry point 0x<number>

Data in Simulator initialization files holds embedded processor core in reset because entry point 0x<number> specified in Hexadecimal (Intel-Format) File does not match embedded processor core's reset address 0x<number>

Data in Simulator initialization files holds embedded processor core in reset because Hexadecimal (Intel-Format) File(s) do not contain initialization data for entry point 0x<number> or entry point is in memory external to Excalibur embedded processor stripe

data input port of the SERDES transmitter ATOM <name> must have the same width value as the CHANNEL_WIDTH parameter

Data source error: illegal value <text> for <name> parameter

Data source error: illegal value <text> for <name> parameter

DATA[0] dual-purpose pin not reserved

Database file <name> corrupted. Database error: <text>

Database file <name> corrupted. Database error: <text>

Database file <name>, created by Quartus II <version number> software, not compatible with current Quartus II <version number> software

Database file <name>, created by Quartus II <version number> software, not compatible with current Quartus II <version number> software

Database file is incompatible with current version of Quartus II software -- replaced file with new version of file

Database purge was <successful, NOT successful, stopped, or canceled due to an error>

datain input port of GXB receiver channel atom <name> must be fed by input pin

datain input port with value <number> of the GXB transmitter channel atom <name> must be the same width as CHANNEL_WIDTH parameter with value <number>

datain port of HSDI receiver ATOM <name> must be fed by input pin that does not feed any other logic

dataout pin <name> of HSDI transmitter fed by PLL <name> is assigned <name> I/O standard but dataout pin <name> of another HSDI transmitter fed by the same PLL is not assigned the same I/O standard

dataout port of GXB transmitter channel atom <name> must fan out to only one output pin

dataout port of HSDI transmitter ATOM <name> must fan out to only one output pin

DDR pin group must have at least two registers that generate signal that feeds output enable port of DQS or DQ I/O pin <name>

DDR pin group must have output of DQ I/O pin <name> to device that feeds datain port of at least two registers

DDR pin group must have registers feeding DQ I/O pins driven by DQS I/O pin <name> that are clocked by same PLL output signal

DDR pin group must have registers feeding DQS I/O pin <name> and its associated DQ I/O pins that are clocked by same PLL

Dedicated clock cannot feed I/O pin <name> in both positive and negative polarities

Dedicated clock cannot feed I/O pin <name> that feeds I/O cells in both positive and negative polarities

Dedicated clock cannot feed I/O pin <name> that feeds periphery in both positive and negative polarities.

Dedicated clock input pin <name> cannot feed I/O cells both positively and negatively

Dedicated clock pin <name> assigned to node <name>

Dedicated fast I/O pins are used with VREF-dependent I/O standard, but neighboring I/O bank has incompatible I/O standards

Defaults Statement must be first item in Logic Section

Delay <delay> is out of acceptable range

Delay <number> on node <name> is illegal -- legal values for the delay are between <number> and <number>

Delay chain <number> contains <number> node(s)

Delay from clock to LVDS transmitter clock output <name> is <time>

Delay from clock to LVDS transmitter data output <name> is <time>

Delay from SignalProbe source signal <name> to output pin <name> at location <name> is <number> ps

Delay of LVDS transmitter PLL <name> is <delay>

Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two

Delay setting of <number> ps on DQS I/O pin <name> is out of range -- Fitter reset to <number> ps

Deleting a node or entity from LogicLock region <name> also deletes all back-annotated node locations in this region and its descendant LogicLock regions. Do you want to delete the node or entity?

Deleting selected assignment also deletes all back-annotated assignments in LogicLock region <name>. Do you want to delete the selected assignment?

Demoted back-annotated node location on node <name> assigned to LogicLock region <name> from <location> to <location>

Demoted location assignment <name> on embedded cell <name> to EAB location <name>

Demoted location assignment to embedded cell <name> to ESB

Design <name>: <type> <was or were> <completed, failed, or stopped>. <number> error <name>, <number> warning <name>

Design <name>: <type> <was or were> <completed, failed, or stopped>. <number> error<name>, <number> warning<name>

Design <name>: <type> <was or were> <completed, failed, or stopped>. <number> error<name>, <number> warning<name>

Design Assistant information: <Nodes with high fan-out>. Found <number> node(s) with high fan-out.

Design Assistant Information: <Register output directly drives input of another register when both registers are triggered at same time>. Found <number> shift register structure(s) related to this rule.

Design Assistant Information: <Registers in direct data transfer between clock domains are triggered by clock edges at the same time>. Found <number> structure(s) related to this rule.

Design Assistant information: Design Assistant does not support target <name> device. Can't launch Design Assistant.

Design Assistant information: finished post-fitting analysis of current design -- generated <number> information messages and <number> warning messages

Design Assistant information: finished post-synthesis analysis of current design -- generated <number> information messages and <number> warning messages

Design Assistant requires full compile

Design Assistant warning: <All data bits that are transferred between asynchronous clock domains are synchronized>. Found <number> structure(s) related to this rule.

Design Assistant warning: <Asynchronous load should be directly supported by one logic cell>. Found <number> asynchronous load structures related to this rule.

Design Assistant warning: <Clock signal should be a global signal>. Found <number> node(s) related to this rule.

Design Assistant warning: <Clock signal source should drive only input clock ports>. Found <number> nodes related to this rule.

Design Assistant warning: <Data bits are not correctly synchronized when transferred between asynchronous clock domains>. Found <number> structure(s) related to this rule.

Design Assistant warning: <Data bits are not synchronized when transferred between asynchronous clock domains>. Found <number> structure(s) related to this rule.

Design Assistant warning: <Design should not contain combinatorial loops>. Found <number> combinatorial loop(s) related to this rule.

Design Assistant warning: <Design should not contain delay chains>. Found <number> delay chains.

Design Assistant warning: <Design should not contain latches>. Found <number> latch(es) related to this rule.

Design Assistant warning: <Design should not contain SR latches>. Found <number> SR latch(es) related to this rule.

Design Assistant warning: <External reset should be correctly synchronized>. Found <number> node(s) related to this rule.

Design Assistant warning: <External reset should be synchronized using two cascaded registers>. Found <number> node(s) related to this rule.

Design Assistant warning: <Gated clock should be implemented according to Altera standard scheme>. Found <number> node(s) related to this rule.

Design Assistant warning: <Gated reset should be synchronized>. Found <number> node(s) related to this rule.

Design Assistant warning: <Gated reset that is generated in one clock domain and used in other, asynchronous clock domains should be correctly synchronized>. Found <number> node(s) related to this rule.

Design Assistant warning: <Gated reset that is generated in one clock domain and used in other, asynchronous clock domains should be synchronized>. Found <number> node(s) related to this rule.

Design Assistant warning: <Input clock pin should fan out to only one gated clock>. Found <number> input clock pins related to this rule.

Design Assistant warning: <Inverter should not be implemented in logic cell>. Found <number> node(s) related to this rule.

Design Assistant warning: <Multiple pulses should not be generated in design>. Found <number> structure(s) related to this rule.

Design Assistant warning: <Only one VREF pin should be assigned to HardCopy test pin in an I/O bank>. Found <number> I/O banks where the following VREF pins are assigned to the following HardCopy test pins.

Design Assistant warning: <Pulses should be implemented according to Altera standard scheme>. Found <number> pulse generator(s) related to this rule.

Design Assistant warning: <Register output should not drive register's control signal directly or through combinatorial logic>. Found <number> combinatorial loops related to this rule.

Design Assistant warning: <Registers are triggered by different edges of same clock>. Found <number> structures related to this rule.

Design Assistant warning: <Reset signal source should drive only input reset ports>. Found <number> node(s) related to this rule.

Design Assistant warning: <Two or more register outputs in cascade should not directly drive clock ports of following registers>. Found <number> structures related to this rule.

Design Assistant was <successful, NOT successful, stopped, or canceled due to an error>

Design compiled for <name> device, but quartus.ini file specifies use of <name> bitstream

Design Compiler software error: <text>

Design Compiler software information: <text>

Design Compiler software warning: <text>

Design contains <number> embedded cells, but the device can only contain <number> embedded cells

Design contains <number> input pin(s) that do not drive logic

Design contains <number> user assigned cells

Design contains <number> virtual pins

Design contains combinatorial loop of <number> nodes. Estimating the delays through the loop.

Design contains non-registered write enable <name>. Random data may be written to it during initialization.

Design contains too many Clocklock PLLs

Design contains too many row-global signals

Design contains too many row-global signals in a row

Design entity name <name> exceeds <number> character limit

Design file <name> already exists. Do you want to update it?

Design file contains illegal characters for Verilog HDL

Design has <number> percent of logic elements back-annotated -- can't perform fitting netlist optimizations when more than <number> percent of LEs are back-annotated

Design name <name> is illegal for Verilog HDL

Design name <type_name> is illegal for VHDL

Design name for <name> contains a number -- illegal for Verilog HDL and VHDL -- adding "\\" in front of name

Design requires <number> <name> resources -- too many to fit in <number> available in the selected device or any device in the device family

Design requires <number> global clear signals, but the selected device can contain only <number> global clear signals

Design requires <number> global clock signals, but the selected device can contain only <number> global clock signals

Design requires <number> global Output Enable signals, but the selected device can contain only <number> global output enable signals

Design requires <number> I/O pins, but the selected device can contain only <number> I/O pins

Design requires <number> I/O pins, including <number> reserved pins, but the selected device can contain only <number> I/O pins

Design requires <number> LABs, but device contains only <number> LABs -- attempting to pack register-only logic cells with combinatorial logic cells

Design requires <number> logic cells, but target device can contain only <number> logic cells

Design requires <number> macrocells, but the selected device can contain only <number> macrocells

Design requires <number> output enable signals, but the device can contain only <number> output enable signals

Design requires <number> output pins if the Fitter uses all current parallel expanders, but the selected device can contain only <number> output pins

Design requires <number> output pins, but the selected device can contain only <number> output pins

Design requires <number> output pins, including <number> Output Enable signals implemented in logic cells, but the selected device can contain only <number> output pins

Design requires <number> output pins, including <number> reserved pins, but the selected device can contain only <number> output pins

Design requires <number> shareable expanders, but the device can contain only <number> shareable expanders

Design requires too deep dual-port RAM to fit in the selected device or any device in the device family

Design requires too deep dual-port RAM to fit in the selected device or any device in the device family

Design requires too large dual-port RAM to fit in the selected device or any device in the device family

Design requires too many <name> resources to fit in the selected device or any device in the device family

Design requires too many <number> global output enable and global clock signals, but the selected device can contain only <number> global output enable and global clock signals

Design requires too many device routing resources: overall column FastTrack interconnect <number>%%; overall row FastTrack interconnect <number>%%; maximum column FastTrack interconnect <number>%%; maximum row FastTrack interconnect <number>%%

Design requires too many dual-port RAM blocks to fit in the selected device or any device in the device family

Design requires too many embedded processors to fit in the selected device or any device in the device family

Design requires too many I/O pins to fit in the selected device or any device in the device family

Design requires too many logic cells to fit in target device or any device in target device family

Design requires too much RAM to fit in the selected device or any device in the device family

Design requires too wide dual-port RAM to fit in the selected device or any device in the device family

Design requires too wide dual-port RAM to fit in the selected device or any device in the device family

Design uses <number> DSP blocks, but only <number> DSP blocks are available in the device

Design uses enable input pin <name> and enable input pin <name>, but only one enable input pin can be used in <name> device family

Destination <name> has maximum output frequency of <number> for specified <name> I/O standard or internal clock network

Destination <name> may be non-global or may not use global clock

Destination of the <type> port of ClockLock PLL <name> cannot be inverted

Detected clock network of 1000 or more paths -- Clock path will not be displayed

Detected combinatorial loop in register <name> at time <time> -- set output to X

Detected more than <number> mismatched levels -- stopped comparison

Detected transition on scanclk port of PLL <name> at time <time> during PLL quiet mode -- PLL may not function correctly

Detecting <name> as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as <name>

DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back

Device <name> does not belong to device family <name> -- choosing an appropriate device from the available devices. Altera recommends removing all location assignments when changing the device -- do you want to remove all location assignments?

Device <name> does not support <name> file type

Device <name> does not support selected mode

Device <name> is illegal. Choose a legal device.

Device <name> is not supported

Device <name> selected for replacement is incompatible with current device <name> associated with programming file. Proceeding will cause programming file to disappear from File list in Programmer window. Do you want to replace current device with new device?

Device <name> selected for replacement is incompatible with current device <name>. Devices cannot be replaced in chain when it is in Passive Serial mode.

Device <name> used in the creation of the Routing Constraints File and the current device do not match -- turning off constrained routing

Device <number> contains JTAG ID code 0x<number>

Device block <name> in System Build Descriptor File must contain family parameter

Device block in System Build Descriptor File cannot be used because <text>

Device chain in Programmer window does not match physical device chain -- expected <number> device(s) but found <number> device(s).

Device chain in use

Device configuration canceled

Device configuration is in progress. You must stop configuration before closing Programmer window.

Device did not accept configuration data (after <number> bits sent)

Device family <name> does not support LogicLock regions

Device family <name> does not support SignalTap II incremental routing

Device family <name> is illegal. Specify a legal device family

Device family <name> is not available with the Quartus II Web Edition license

Device family <name> is not available with the Quartus II Web Edition license

Device family does not support Amplify as an EDA resynthesis tool

Device family does not support formal verification

Device family is not supported by the PALACE software

Device family selection has changed. Do you want to allow the Compiler to select a device automatically from the available devices and remove any pin assignments?

Device index <number> is not associated with a specified programming file

Device migration enabled -- compilation may have failed due to additional constraints when migrating

Device name <name> already exists

Device number <number> failed to configure in passive serial chain

Device or configuration device <name> is not IEEE-1532 compliant

Device or device family does not support LogicLock regions

Device requires opposite polarity of global signal for this port -- invert INPUT pin <pin name> that feeds the secondary input of primitive <primitive name>

Device selection has changed -- previous device and new device have similar pin-outs. Do you want to convert pin assignments from the previous device to the new device?

Device selection has changed. You must recompile before starting the Design Assistant.

Device selection has changed. You must recompile before starting HardCopy file generation.

Device selection has changed. You must recompile before starting the timing analysis.

Device takes up to 256 clock cycles to train dedicated DDR I/O circuitry to generate correct DQS phase shift on system power-up

Device without X in device name cannot be selected for project with HSDI PLLs

Device-wide I/O standard setting <name> not supported for selected device family

Devices selected for migration have different speed grades -- frequency limits are checked only for current device, not all devices

Didn't assign pin <name> to node <name>

Differential I/O pin <name> with open-drain option turned on is illegal

Differential I/O pin <name> with open-drain option turned on is illegal

Differential I/O standard <name> assigned to <name> pin of PLL <name> is illegal

Differential I/O standard assigned to pin <pin>, but location must be assigned

Directory <name> does not exist. Do you want to create it?

Directory <name> does not exist. Do you want to create it?

Disable option available for <type> assignments only -- do you want to disable <type> assignments?

Disk is full

Disk is full -- current compilation halted

Disk is full -- current compilation halted

Disk is full -- stopped compilation

Disk space full error at Logic Synthesizer stage <text>: <text>

Display a maximum of 3000 critical paths in Floorplan Editor

Do you want the Quartus II software to automatically check for product updates and new Quartus II information at startup? Altera recommends that you check for updates and new Quartus II information. If you are running the Quartus II software on a UNIX or Linux workstation, you must specify your web browser's location. You can turn the software update and information options on or off at any time on the Internet Connectivity page of the Options dialog box.

Do you want to add file <name> to current project?

Do you want to apply changes before back-annotating?

Do you want to check the Altera web site for updates? (Please allow a little time for the Quartus II software to make the connection.)

Do you want to close current project <name>?

Do you want to confirm each time before connecting to the Internet? You can turn the Confirm before connecting to web option on or off at any time on the Internet Connectivity tab of the Options dialog box.

Do you want to create a new project now?

Do you want to create a new project with this file?

Do you want to disable all assignments?

Do you want to overwrite database that was created by Quartus II <number>? It has an incompatible format. This action will not affect your design files or other source files. If you do not want to overwrite the database, you must use the same Quartus II software version to open it.

Do you want to overwrite database? It has an incompatible format. This action will not affect your design files or other source files. If you do not want to overwrite the database, you must use the same Quartus II software version to open it.

Do you want to remove I/O standard assignments?

Do you want to save changes to assignments?

Do you want to save changes to assignments?

Do you want to save changes to current Compiler settings <name>? You cannot undo this change.

Do you want to save changes to current Simulator settings <name>? You cannot undo this change.

Do you want to save changes to current software build settings <name>? You cannot undo this change.

Do you want to save changes to project settings before opening the web browser?

Do you want to stop the current process?

Down spread value <number>% is greater than <number>%

DQS Delay and DQS Frequency logic options must be specified for DQS I/O pin <name>

DQS I/O and DQ I/O groups driven by different clocks must be placed on different sides of device

DQS I/O and DQ I/O groups driven by the same clock must be placed on same side of device.

DQS I/O pin <name> driven by different system clock than other DQS I/O pins in its DDR pin group

DQS I/O pin <name> has too many fan-outs -- only <number> fan-outs allowed

DQS I/O pin <name> must be DDIO output

DQS I/O pin <name> must be driven by same PLL output as other DQS I/O pins in its group

DQS I/O pin <name> must drive DQ I/O pin clocks

DQS I/O pin <name> must have combinatorial inputs into the device

DQS I/O pin <name> must have registered outputs driving out of the device

DQS I/O pin <name> must have same DQS Phase Shift setting as other DQS I/O pins in its group

DQS I/O pin <name> must have same frequency as the other DQS I/O pins in its group

DQS I/O pin and its corresponding DQ I/O pins are driven by different clocks, but a PLL is used on each pin to generate the frequency or phase shift

DQS input reference clock of DQS I/O pin <name> must be an input clock pin

DQS or DQ I/O <name> <name> must be assigned to top or bottom of device

DQS Phase Shift setting on DQS I/O pin <name> must be 72 or 90 degrees

DQS Phase Shift, DQS Frequency, and DQS Input Reference Clock logic options must be specified for DQS I/O pin <name>

DSP block <name> has <number> <name> signals, but only <number> are allowed

DSP block <name> has <number> <name>/<name> signal pairs, but only <number> are allowed

DSP block <name> has <number> slices in mode <name>, but only <number> are allowed

DSP block <name> has cells with different base widths

DSP block <name> has cells with different modes

DSP block 18-bit multplier <name> assigned to location <name> with illegal index

DSP block input shift register starting with <name> of <name> must use same clock and clock enable signals

DSP block multiplier node <name>

DSP block multiplier node <name>

DSP block multiplier WYSIWYG primitive <name> has <name> port that cannot be used in 36_BIT_MULTIPLY mode

DSP block multiplier WYSIWYG primitive <name> has dataout port that must drive a data port of a DSP block output WYSIWYG primitive

DSP block multiplier WYSIWYG primitive <name> has dataout port that must drive a DSP block output WYSIWYG primitive

DSP block multiplier WYSIWYG primitive <name> has dataout[<index>] port that cannot be floating

DSP block multiplier WYSIWYG primitive <name> has dataout[<index>] port that must drive only one port

DSP block multiplier WYSIWYG primitive <name> has dataout[<index>] port that must drive the same bit index on the data port of a DSP block output WYSIWYG primitive

DSP block multiplier WYSIWYG primitive <name> has dataout[<index>] port that must drive the same data port of a DSP block output WYSIWYG primitive

DSP block multiplier WYSIWYG primitive <name> has dataout[<index>] port that must drive the same node for all bits

DSP block output node <name>

DSP block output WYSIWYG primitive <name> has <name> port that must be driven by a DSP block multiplier WYSIWYG primitive

DSP block output WYSIWYG primitive <name> has <name> port that must be driven by the dataout port of a DSP block multiplier WYSIWYG primitive

DSP block output WYSIWYG primitive <name> has <name>[<index>] port that must be driven by the dataout port of a DSP block multiplier WYSIWYG primitive

DSP block output WYSIWYG primitive <name> has <name>[<index>] port that must be driven by the same bit index on the dataout port of a DSP block multiplier WYSIWYG primitive

DSP block output WYSIWYG primitive <name> has <name>[<index>] port that must be driven by the same node for all bits

DSP block output WYSIWYG primitive <name> has accoverflow port that must be used in ACCUMULATOR mode

DSP block slice in <name> mode with output node <name>

DSP block slice with DSP block output node <name>

DSP block WYSIWYG primitive <name> has input port <name>[<index>] that cannot be floating

DSP block WYSIWYG primitive <name> has unconnected port <name>[<bit number>] -- port must be connected because corresponding register is used

Dual purpose pin <name> assigned to location <name> has illegal location assignment

Dual-range group name in Text Design File contains an illegal character

Duplicate LATCH primitives merged into single LATCH primitive

Duplicate LATCH primitives merged into single LATCH primitive <name>

Duplicate registers merged to single register

Duplicate registers merged to single register <name>

Duplicate registers merged to single register <name>, power-up level has changed

Duplicating node <name> -- node is fed by or drives an I/O node

Duplicating node <name> -- asynchronous clear port on node is used

Duplicating node <name> -- asynchronous clock enable port is used

Duplicating node <name> -- asynchronous data port on node is used

Duplicating node <name> -- asynchronous load port on node is used

Duplicating node <name> -- node directly drives a global signal

Duplicating node <name> -- node directly drives an asynchronous signal

Duplicating node <name> -- node feeds or is driven by an I/O node

Duplicating node <name> -- node has only one fan-out

Duplicating node <name> -- node is on a path that crosses clock domains

Duplicating node <name> -- node is on a path with a timing assignment

Duplicating node <name> -- node is set to Always Allow

E

EDA design entry or synthesis tool was not specified. Detecting EDA tool <name> as the tool that generated the EDIF Input File.

EDA tool error: <text>

EDA tool error: <text>

EDA tool information: <text>

EDA tool information: <text>

EDA tool warning: <text>

EDA tool warning: <text>

EDIF Input File cannot contain undefined parameter <text> for node <name>

EDIF Input File contains more than one definition for the <name> construct

EDIF Input File has port <name> bit that is not in bit range for the port

EDIF version and level are not supported

EDIF view type <name> not supported

Embedded cell <name> in deep RAM mode requires <number> RAM bits, but the device allows only <number> RAM bits

Embedded cell <name> requires <number> secondary signals of type <type>, <type>, and <type>, but the device allows only <number> signals

Embedded cell <name> requires <number> secondary signals of type <type>, <type>, and <type>, but the selected device allows only <number> secondary signals

Embedded System Block ATOM <name> cannot have more than two clear signals, or more than one clear signal per port

Embedded System Block ATOM <name> cannot have more than two clock signals or two clock enable signals, or more than one clock signal or one clock enable signal per port

Enable Bus-Hold Circuitry and Weak Pull-Up Resistor logic options are specified for instance <name>. Only Enable Bus-Hold Circuitry will be used for this instance.

Enable Bus-Hold Circuitry and Weak Pull-Up Resistor logic options cannot both be enabled for <name> pin

Enable Bus-Hold Circuitry and Weak Pull-Up Resistor logic options cannot both be enabled for <name> pin

Enable Bus-Hold Circuitry and Weak Pull-Up Resistor logic options cannot both be enabled for <name> pin

Enable Bus-Hold Circuitry and Weak Pull-Up Resistor logic options cannot both be enabled for <name> pin

Enable input of ClockLock PLL <name> must be driven by input pin

Enable input port of PLL <name> must be driven by input pin

enable0 input port of the SERDES receiver ATOM <name> is driven by an invalid port -- enable0 input port must be driven by a valid enable output port of a fast PLL

enable0 input port of the SERDES transmitter ATOM <name> is driven by an invalid port -- enable0 input port must be driven by a valid enable output port of a fast PLL

enable0 output port of fast PLL <name> must feed only enable0 input port of a SERDES receiver

enable1 input port of the SERDES receiver ATOM <name> is driven by an invalid port -- enable1 input port must be driven by a valid enable output port of a fast PLL

enable1 output port of fast PLL <name> must feed only the enable1 input port of a SERDES receiver or the enable0 input port of a SERDES transmitter

ENABLE_SYNCH_INPUT_REGISTER_1S25 option is turned <text>

Enabled smart compilation

Encoded state bit <name>

Encoding result for state machine <name>

Encountered unknown disk error while writing to file <name>

End of document reached

End time not specified in vector source file <name> -- setting end time to 1 ps

Enhanced PLL <name> has <name> port with duty cycle value <number> -- for the lock filter to function correctly, the duty cycle value must be more than 40% or less than 60%

Enhanced PLL <name> has the following parameter warnings

Enhanced PLL <name> uses inclk0 and inclk1 ports, but clkswitch port is unconnected, and SWITCH_OVER_ON_LOSSCLK and SWITCH_OVER_ON_GATED_LOCK parameters are set to OFF

Enter name of symbol to insert

Entity <name> is already assigned to LogicLock region <name>. Do you want to reassign this entity to a new LogicLock region?

Entity <name> is instantiated by entity <name>

Entity <type> doesn't have name

Entity name <name> conflicts with Quartus II primitive name

Entry point specified in Hexadecimal (Intel-Format) File <name> is 0x<number>, but must match previously specified entry point or embedded processor core's reset address 0x<number>

Erasing <name> configuration device(s)

Erasing device <number>

Error in file <name> at line <name> and column <name> -- <text>

Error occured while initializing or parsing file : <name>

Error on line number <number> in Routing Constraints File

Estimated most critical path is <register or pin> to <register or pin> delay of <time>

Evaluated function <name> cannot be defined more than once

Evaluated function <name> contains <number> arguments, but must contain <number> arguments

Examining device <number>

Examining devices

Excalibur <name> stripe signal <name> not routed correctly

Excalibur shared I/O output enable assigned to <name> must drive only shared I/O pin

Excalibur signal <name> must be assigned to pin <name>

Excalibur signal <name> must be assigned to pin <name>, but pin <name> has user assignment

Expansion Bus Interface zero memory region at address [0x<number>, 0x<number>] does not have enough space for 0x<number> bytes of boot data generated

Expansion Bus Interface zero memory region must be mapped

Export focus contains an illegal character -- specify an export focus containing only legal characters

Expression passed to LOG2 is negative or zero

Expression to the left of period (.) must be symbolic name for megafunction, macrofunction, primitive, or state machine

Expression to the left of period (.) must be symbolic name for megafunction, macrofunction, primitive, or state machine

Expressions do not support array notation

External clock ports of enhanced PLL <name> are driving <number> pairs of output pins -- external clock ports cannot feed more than four pairs of output pins

External clock ports of enhanced PLL <name> are driving <number> pairs of output pins -- they must not feed more than four pairs of output pins

External feedback input port of ClockLock PLL <name> must be driven by input pin

External text editor can operate only after you close all text files opened in Quartus II Text Editor windows

F

Failed to generate Tcl Script File (.tcl) for EDA <type> tool

Failed to place XGMII state machine <name> at location <name> as more than <number> globally routed signals feed into IO clock region (<number>,<number>) to (<number>,<number>)

Failed to route <number> signal(s)

Failed to route the following <number> signal(s)

Fan-in of WYSIWYG ClockLock PLL primitive <name> can fan-out only to WYSIWYG ClockLock PLL primitives with the same input frequency value

Fan-in of WYSIWYG ClockLock PLL primitive <name> cannot feed more than two destinations

Fan-out node <name>, from combout port of DQS I/O pin <name>, must be DDIO bidirectional pin

Fast or enhanced PLL clock output port <name> has illegal Global Signal logic option setting (<type>) -- must be set to Global Clock or Regional Clock

Fast Passive Parallel chain cannot contain both Stratix and APEX II devices

Fast PLL <name> does not use the comparator input port, but the enable0 and enable1 outputs must come from the same counter

Fast PLL <name> drives differential I/O nodes and has division value set to <number>, but should be the same as deserialization value <number>

Fast PLL <name> has <number> Mbps differential I/O data rate, but can support only <number> Mbps differential I/O data rate

Fast PLL <name> has Global Clock setting assignment on core clock output

Fast PLL <name> uses the comparator input port, but the enable0 and enable1 outputs must come from different counters

fbin port must not be connected when ClockLock PLL <name> is not in external feedback mode

fbin port used by <ClockLock PLL> <name> is not supported

Feature <name> is not available with your current license

Feature <name> is not available with your current license, or license does not exist

Feature <name> is not supported for target device

Feature <text> is unsupported for simulation

Feedback to ClockLock PLL permitted only when OPERATION_MODE parameter is set to EXTERNAL_FEEDBACK

File <name>

File <name> already exists. Do you want to overwrite it?

File <name> batch mode was left open from the last script execution. Add an end_batch function to the Tcl script.

File <name> contains error at line <number>

File <name> contains time-limited core -- Vendor: 0x<name>, Product: 0x<name>

File <name> contains time-limited cores

File <name> does not exist. Do you want to create it?

File <name> does not exist. You must create this file or specify a different file name before you simulate the design. Do you want to specify a different file name?

File <name> is a MAX+PLUS II Graphic Design File. Saving to this file now will overwrite it in Quartus format, which cannot be read by MAX+PLUS II.

File <name> is a Quartus II version 1.1 or earlier file. Overwrite the file in current Quartus II format?

File <name> is corrupted

File <name> is not a Quartus-generated file. Placed the <type> code for this block at the end of the design file.

File <name> is not a recognized design file type

File <name> is not a valid SignalTap II File

File <name> is read-only

File <name> is read-only

File <name> must be a valid Slave Binary Image File

File <name> was changed outside the Quartus II software, or was rewritten due to an error in a settings and configuration file. Do you want to reload the file, losing some or all of the modifications you made since opening the file?

File <name> was changed outside the Quartus II software. Do you want to reload the file, possibly overwriting portions of the file, including any saved changes?

File <name> was changed outside the Quartus II software. Do you want to save the file using this file name, possibly overwriting some or all of the changes made to the file outside the Quartus II software?

File cannot contain SRAM Object Files with both remote update and local update enabled

File details of compared files do not match

File details of compared files do not match

File with name <name> already exists. Do you want to overwrite it?

Final fitting attempt was unsuccessful

Finished creating Jam File(s), Jam Byte-Code File(s), Serial Vector Format File(s), or In System Configuration File(s)

Finished generating file(s)

Finished searching document

Finished searching document

Finished searching document. No replacements made.

Finished searching document. Can't find search text.

Finished searching document. Replaced <number> occurrences of text <text> with replacement text <text>.

Finished searching document. Replaced <number> occurrences of text <text> with replacement text <text>.

Fitter cannot find solution after user assignment

Fitter created <number> LABs, but the device can only contain <number> LABs

Fitter needs to place <number> <name>

Fitter needs to place <number> <name>, <number> of which cannot be placed on dedicated fast pins

Fitter needs to place <number> <name>, <number> of which cannot be placed on the dedicated clock pins

Fitter needs to place <number> <name>, because <number> of the pins cannot be placed on dedicated fast or dedicated clock pins

Fitter optimization settings are on -- do you still want to back-annotate?

Fitter placement was successful

Fitter requires <number> LABs to implement the project, but device contains only <number> LABs

Fitter requires that more entities of type <type> be placed in a region than are available in the region

fitter sub-command <command> not recognized.

Fitter used dedicated clock pin <name>

Fitter used dedicated clock pin <name> for ClockLock PLL placement

Fitter used dedicated fast pin <name>

Fitter used dedicated fast pin <name> for ClockLock PLL placement

Fitter used I/O pin <name> to place node <name>

Fitting attempt failed -- retrying

Fitting design with smaller device may be possible, but smaller device must be specified

Fixed size LogicLock region <name> is not tall enough for its contents. It must be at least <number> LABs tall, but is only <number> LABs tall.

Fixed size LogicLock region <name> is not wide enough for its contents. It must be at least <number> LABs wide, but is only <number> LABs wide.

FLEX 6000 devices can only be bypassed without any programming action performed on them

FLEXlm software error: <text>

Fmax must be greater than zero

fmax restricted to <time> pin edge rate <time>. Expand message to see actual delay path.

fmax restricted to Clock High delay (<time>) plus Clock Low delay (<time>) : restricted to <time>. Expand message to see actual delay path.

Following node assigned to LogicLock region or custom region -- ignored Output Enable Register Duplication assignment on node

Following nodes are assigned to locations or regions, but do not exist in design

Following nodes assigned to LogicLock region or custom region -- can't optimize I/O cell register placement for these nodes

Following nodes assigned to LogicLock region or custom region -- ignored Fast Input Register, Fast Output Register, or Fast Output Enable Register assignments

Following nodes assigned to LogicLock region or custom region -- ignored Fast Input Register, Fast Output Register, or Fast Output Enable Register assignments on nodes

Following nodes assigned to LogicLock region or custom region -- ignored Fast Input Register, Fast Output Register, or Fast Output Enable Register assignments on nodes

Following nodes have location assignments

For fast PLL <name> comparator input port is not synchronized to the core clock

For Generate Statement generates <number> instances of megafunction, macrofunction, or primitive, but Instance Declaration contains only <number> instance names

Formal verification may give mismatches -- Allow register retiming to trade off Tsu/Tco with Fmax is turned on

Formal verification may give mismatches -- Automatically duplicate logic elements is turned on

Formal verification may give mismatches -- Perform gate-level register retiming is turned on

Formal verification may give mismatches -- Perform WYSIWYG primitive resynthesis is turned on

Format of base number <number> is illegal

Found <number> <type> blocks in design -- only one <type> block is allowed

Found <number> design units and <number> entities in source file <name>

Found <number> LogicLock regions

Found Altera-specific megafunction, primitive or component <name>

Found clear pulse width violation at time <time> on register <name>

Found clock <text> time violation at <time> on register <name>

Found clock-sensitive change during active clock edge at time <time> on register <name>

Found combinatorial loop of <number> nodes

Found complex timing assignments. Calculating slack delays instead of fmax.

Found conflicting assignments on node <name>

Found debug hub <name> in the design -- ignoring assignments for debug hub

Found design unit <name>: <name>

Found entity <name>: <name>

Found extra JTAG WYSIWYG primitive <name>

Found glitch at time <time> of duration <range> on node <name>

Found hold time violation at time <time> on Embedded System Block input <name>, signal <name> with respect to write enable <name>

Found hold time violation at time <time> on register <name>

Found hold time violation between source pin or register <name> and destination pin or register <name> for clock <name> (Hold time is <time>)

Found hold time violation between source pin or register <name> and destination asynchronous memory <name> for clock <name> (Hold time is <time>)

Found illegal complex timing assignment(s)

Found illegal I/O standard on PLL enable pin <name>

Found inconsistent dimensions

Found inconsistent I/O type or default value

Found logic contention at time <time> on bus node <name>

Found LogicLock region assignments on the following nodes

Found long entity name <name> -- unable to process entity due to size limit

Found multiple base names

Found mutually dependent clocks -- excluding clocks from some parts of timing analysis

Found pins functioning as undefined clocks and/or memory enables

Found preset pulse width violation at <time> on register <name>

Found read pulse active width violation at time <time> on Embedded System Block <name>

Found remote update block in design, but Configuration mode not Remote

Found setup time violation at time <time> on Embedded System Block <name> signal <name> with respect to write enable <name>

Found setup time violation at time <time> on register <name>

Found the following redundant logic cells in design

Found the following redundant logic cells in design

Found unknown error in a Block Symbol File <name>

Found unused connectors

Found write pulse active width violation at <time> on Embedded System Block <name>

Found write pulse inactive width violation at time <time> on Embedded System Block <name> -- simulation results may be incorrect

FPGA Express, FPGA Compiler II, or FPGA Compiler II Altera Edition software error: <name> <text>

FPGA Express, FPGA Compiler II, or FPGA Compiler II Altera Edition software information: <name> <text>

FPGA Express, FPGA Compiler II, or FPGA Compiler II Altera Edition software warning: <name> <text>

Full compilation was <successful, NOT successful, stopped, or canceled due to an error>

Full compilation was <successful, NOT successful, stopped, or canceled due to an error>

Function <name> of instance <name> not used

Function <number> in LUT is illegal

Function with value <number> in LUT cannot be empty

G

Generate HardCopy files was <successful, NOT successful, stopped, or canceled due to an error>

Generated Binary File <name>

Generated boot data file <name>

Generated files <name>.vho and <name>_vhd.sdo for <type> EDA tool

Generated files <name>.vo and <name>_v.sdo for <type> EDA tool

Generated files <name>_board.data and <name>_board.mod

Generated files <name>_chip.data and <name>_chip.mod

Generated flash programming file <name>

Generated Hexadecimal (Intel-Format) File <name>

Generated IBIS Output File <name> for board level analysis

Generated Library File <name>

Generated Motorola S-Record File <name>

Generated passive programming files

Generated scan chain Memory Initialization File <name> for PLL <name>

Generated uPCore Transaction Model Output File <name>

Generated Verilog Test Bench File <name> for simulation

Generated VHDL Test Bench File <name> for simulation

Generating HardCopy files requires full compile

Generating IBIS Output File with typical RLC values -- RLC minimum and maximum values are unavailable

Generating resynthesis output files. Do you want to continue?

GLOBAL buffer <primitive name> must be driven by an INPUT pin or a GLOBAL buffer

Global clear pin <name> assigned to <name> has illegal location

Global clock pin <name> assigned to <name> has illegal location

Global option <name> has value <text>

Global output enable pin <name> assigned to <name> has illegal location

Global signal <name> does not exist on conduit

Global signal <name> uses non-global resources to destination <name>

Global Signal logic option for cell <name> cannot be set to Off when cell is assigned to dedicated clock pin

Global Signal logic option set to Off for clock signal <name> -- setting not recommended for clock signals entering or leaving quad

Global signal logic option setting <name> assigned to fan-outs

Global Signal logic option setting <name> from region(<number>, <number>) to (<number>, <number>) may be available

Global signals use non-global resources to route global signals

GPIO <number>-bit data width is not valid for device <name>

GPIO <number>-bit data width specified in System Build Descriptor File <name> does not match <number>-bit data width in the design

GPIO <number>-bit data width specified in System Build Descriptor File <name> is not valid for device <name>

GPIO port is not available for EPXA10 devices

GPIO port, which is enabled in System Build Descriptor File <name>, is not available on EPXA10 devices

Ground current limit exceeded for device -- electrical specifications may not be met

Group <name> already exists in vector source file <name> -- ignoring second definition

Group <name> cannot be redefined with a different range

Group is used as <name>[<number>..<number>] and defined using a different range order (<name>[<number>..<number>])

Group LSB <name><number> overrides BIT0 = MSB in Options Statement

Group MSB <name><number> overrides BIT0 = LSB in actual or default Options Statement

Group name <name> is missing brackets ([ ])

Group name <name> is missing two sets of brackets ([ ][ ])

Group name in Text Design File must use legal single-range, dual-range, or sequential group name notation

Group or node <name> in arithmetic or logical operation cannot contain don't care value

Group range of arithmetic expression contains negative number <number>, but numbers in group ranges cannot be negative

Groups cannot be assigned to nodes

GTL+ I/O standard and 1.8-V I/O standard cannot be assigned to pins in the same I/O bank

GXB receiver channel atom <name> has either serialfdbk or slpbk input port connected -- both serialfdbk and slpbk input ports must be connected or disconnected

GXB transmitter channel atom <name> cannot use input port <name> when in self test mode

GXB transmitter channel atom <name> cannot use input port <name>[<number>] input port when not in force disparity mode

GXB transmitter channel atom <name> cannot use input port <name>[<number>] when not in 8B/10B mode

GXB transmitter channel atom <name> cannot use input port <name>[1] when not in double data mode

GXB transmitter channel atom <name> cannot use output port <name> when in 8B/10B mode

GXB transmitter channel atom <name> cannot use output port <name>[<number>] when in 8B/10B mode

GXB transmitter channel atom <name> cannot use rdenablesync output port when not in channel 0

GXB transmitter channel atom <name> is in reverse parallel loopback mode, but is driven by GXB receiver channel atom <name>, which is not in reverse parallel loopback mode

GXB transmitter channel atom <name> must have output port <name> with size <number> when in 8B/10B mode

GXB transmitter channel atom <name> must have output port <name> with size <number> when in 8B/10B mode

GXB transmitter channel atom <name> must have source at input port <name>

GXB transmitter channel atom <name> must have source at input port <name>[<number>]

GXB transmitter channel atom <name> must have source at input port <name>[<number>] when in 8B/10B mode

GXB transmitter channel atom <name> must have source at input port <name>[<number>] when in force disparity mode

GXB transmitter channel atom <name> must have source at input port <name>[1] when in double data mode

GXB transmitter or receiver pin <name> does not use 1.5-V PCML I/O standard -- Fitter will automatically assign <name> standard to pin

H

HardCopy File <name> has <number> error and <number> warning messages

HardCopy file generation requires full compile

Height <number> of floating LogicLock region <name> causes region to extend onto pins -- maximum legal height is <number>

Height <number> of floating LogicLock region <name> is too large -- maximum legal height is <number> because region is descendant of LogicLock region <name>

Height <number> of LogicLock region <name> causes this region to exceed the bounds of its ancestor LogicLock region <name> -- maximum legal height is <number>

Height <number> of LogicLock region <name> causes this region to exceed the bounds of the target device -- maximum legal height is <number>

Hexadecimal (Intel-Format) File contains initialization data for Expansion Bus Interface zero memory region at address [0x<number>, 0x<number>] -- makeprogfile utility does not use initialization data to generate boot data file if EBI0 is read-only

Hexadecimal (Intel-Format) File data overlaps SRAM Object File data

Hexadecimal (Intel-Format) File must contain initialization data for entry point 0x<number> -- boot data file cannot be generated

Hexadecimal (Intel-Format) File(s) do not specify entry point--entry point 0x<number> is being used

Hexadecimal (Intel-Format) Files do not contain initialization data for entry point 0x<number>, but data in passive programming files does not hold embedded processor core in reset because entry point is in an Expansion Bus Interface memory region or a programmable logic device memory region

Hexadecimal (Intel-Format) Files, Tabular Text Files, and Raw Binary Files do not support EPC16 configuration device

Hierarchy path is illegal

HSDI input or output pin <name> assigned to use <name> I/O standard, but must use differential I/O standard -- using LVDS I/O standard

HSDI PLL <name> drives <number> HSDI channels at <text>, but only 8 HSDI channels can operate above 1000.0 MHz

HSDI PLL ATOM <name> must have clock source

HSDI PLL clkout output pin <name> assigned to use <name> I/O standard, but must use differential I/O standard -- using LVDS I/O standard

HSDI PLL must drive HSDI receiver or transmitter ATOM <name> when clk port is connected

HSDI Primitive <name> not supported

HSDI receiver ATOM <name> has value <number> that is not within legal range for CHANNEL_WIDTH parameter

HSDI receiver ATOM <name> has value <number> that is out of legal range for CHANNEL_WIDTH parameter when in Clock Data Recovery mode

HSDI receiver ATOM <name> must have clock source

HSDI receiver ATOM <name> must have fan-out at dataout port index <number>

HSDI receiver ATOM <name> must have source at clock1 port

HSDI synchronizer ATOM <name> at datain port index <number> missing source

HSDI synchronizer ATOM <name> cannot be connected to both HSDI receiver and HSDI transmitter at the same time

HSDI synchronizer ATOM <name> drives other logic in addition to its HSDI transmitter at port index <number>

HSDI synchronizer ATOM <name> must be connected to an HSDI receiver or an HSDI transmitter

HSDI synchronizer ATOM <name> must have fan-out at dataout port index <number>

HSDI synchronizer ATOM <name>, which drives one HSDI transmitter, also drives different HSDI transmitter at port index <number> of dataout port

HSDI synchronizer ATOM <name>, which is driven by one HSDI receiver, is also driven by different HSDI receiver at port index <number> of datain port

HSDI transmitter ATOM <name> must have clock source

I

I/O ATOM <name> cannot use clk4 to drive both HSDI receiver PLL and other logic

I/O ATOM <name> cannot use the aclr port and have its POWER_UP_HIGH parameter value set to TRUE

I/O ATOM <name> cannot use the aclr port and have its POWER_UP_HIGH parameter value set to TRUE, or use the preset port and have its POWER_UP_HIGH parameter set to FALSE

I/O ATOM <name>, which has its OPERATION_MODE parameter value set to either OUTPUT or BIDIR, must have data source

I/O bank <number> contains I/O pin <name> with Termination logic option setting <name>, but its OCT_RUP and OCT_RDN pins (<name> and <name>) have been used for another purpose

I/O bank <number> contains input or bidirectional pins with I/O standards that make it impossible to choose a legal VCCIO value for the bank

I/O bank <number> has <number> VREF pins that are assigned to HardCopy test pins

I/O bank cannot contain incompatible PCI I/O standards

I/O bank contains the following HardCopy test pins

I/O cell <name> has 3.3-V PCML or differential LVPECL I/O standards, but is assigned to a pin that does not support these differential I/O standards

I/O cell <name> has differential HSTL I/O standards, but is assigned to a pin that cannot drive a PLL or a global clock network

I/O cell <name> has differential I/O standard, but cannot be assigned to transmitter PLL clock output pin <name> because I/O cell <name> is not the clock output of a transmitter PLL

I/O cell <name> has differential I/O standard, but is assigned to a pin that does not support differential I/O standards

I/O cell <name> is fed by two non-global clocks, but at least one clock must be a global clock

I/O cell <name> will power-up low

I/O cell <name> will power-up low

I/O pin <name> already used by I/O cell <name>

I/O pin <name> assigned to node <name>

I/O pin <name> cannot be used by internal logic because it is assigned to dedicated JTAG pin <name>

I/O pin <name> cannot be used by internal logic because it is assigned to dedicated JTAG pin <name> in target device

I/O pin <name> cannot fan out to internal logic because it is assigned to dedicated HSDI input clock <name>

I/O pin <name> in I/O bank <number> is using an Termination logic option setting <name> that is different from Termination logic option setting <name> used by other I/O pins in that bank

I/O pin <name> uses 1.5-V PCML I/O standard but does not drive GXB pins -- 1.5-V PCML supported only for GXB receiver or transmitter pin, and clock input pin

I/O pin <name> was reserved by node <name> because you reserved it, it is needed for a specific device option, or it is needed for a programming pin

I/O pin <name> with setting <name> assigned to I/O bank <number> but bank does not contain OCT_RUP or OCT_RDN location

I/O pin <name> with Termination logic option setting <name> cannot be placed at OCT_RUP or OCT_RDN pin location <name>

I/O pin <name> with Termination setting <name> in I/O bank <number> using I/O standard <name> has I/O standard incompatible with other I/O pins with Termination logic option settings in that bank using I/O standard <name>

I/O standard <name> cannot be assigned to node <name>

I/O standard <name> for pin <name> is not supported by target device

I/O standard <name> is not supported for selected device family

I/O standard <name> on <name> I/O pin <name> cannot have Termination logic option setting <name>

I/O standard assignment <name> to pin <name> is not supported by device

I/O standard assignment to pin <name> is inconsistent with assignments to other pins in the HSDI receiver or transmitter channels -- use LVDS or LVPECL for all pins

I/O standard setting for individual pin <name> not supported for selected device family -- setting I/O standard for pins according to device-wide I/O standard

I/O types on I/O block and mapping conflict

IBIS model for pin <name> at package pin <name> is not available

Identifier <name> cannot be defined more than once

Ignore assignments for <name>[<number>] because it is an invalid assignment target -- <name> is a single bit, and cannot have members

Ignored <name> assignment on clock <name>

Ignored <name> CARRY buffer(s)

Ignored <name> logic option assignment--illegal setting <value>

Ignored <name> parameter in PLL <name> because counter is set to bypass mode

Ignored <name> timing assignment <name> with value <value> between source node <name> and destination node <name> -- assignment illegal for node(s)

Ignored <number> buffer(s)

Ignored <number> CARRY_SUM buffer(s)

Ignored <number> CARRY_SUM primitive(s) -- cannot place fan-out logic in single logic cell

Ignored <number> CARRY_SUM primitives

Ignored <number> CARRY_SUM primitives -- cannot place fan-in logic in single logic cell

Ignored <number> CARRY_SUM primitives -- logic cell requires more inputs than it can contain

Ignored <number> CASCADE buffer(s)

Ignored <number> EXPANDER buffer(s)

Ignored <number> GLOBAL buffer(s)

Ignored <number> LCELL buffer(s)

Ignored <number> LogicLock region assignments with location assignments

Ignored <number> ROW_GLOBAL buffer(s)

Ignored <number> SOFT buffer(s)

Ignored <wildcard> timing assignment <name> with value <value> to node <name> -- assignment illegal for node

Ignored all clique assignments except LAB clique assignments -- only LAB cliques are supported

Ignored all options except BIT0 in Options Statement -- only BIT0 option is supported

Ignored assignment for clique <name>

Ignored assignment of node <name> of type DFF to pin <name>. Set the Fast Input Register Option or Fast Output Register Option on the pin you want the DFF to be packed with.

Ignored assignment of node <name> to location <name>

Ignored back-annotated location <name> on node <name> in LogicLock region <name> because the LogicLock region is auto-sized

Ignored back-annotated location <name> on node <name> in LogicLock region <name> because this location is not a legal location on the current device

Ignored back-annotated location assignment on node <name> assigned to LogicLock region <name> because location is outside region boundaries

Ignored back-annotated node locations in auto-size LogicLock region <name>

Ignored comparator input port for transmitter-only fast PLL <name>

Ignored custom region and/or LogicLock region assignments for some nodes fed by LVDS receiver logic cell <name>

Ignored custom region and/or LogicLock region assignments for some nodes used by PLL <name>

Ignored Decrease Input Delay to Input Register logic option assignment to DQ I/O pin <name>

Ignored Decrease Input Delay To Input Register logic option on pin <name> -- device does not support the decrease input delay option on pins not associated with a Fast Input Register

Ignored Decrease Input Delay To Internal Cell logic option on pin <name> of device <name> -- Decrease Input Delay To Internal Cell option not supported

Ignored Decrease Input Delay to Internal Cells assignment on input or bidirectional pin <name> because pin fans out to PLL <name>

Ignored Decrease Input Delay to Internal Cells assignment to input or bidirectional pin <name> because pin fans out to SERDES receiver <name>

Ignored Decrease Input Delay to Internal Cells logic option assignment from input or bidirectional pin <name> to destination logic cell <name> because it's a global destination

Ignored Decrease Input Delay to Internal Cells logic option assignment to input or bidirectional pin <name> because pin assigned to fast regional clock <name>

Ignored Decrease Input Delay to Internal Cells logic option assignment to input or bidirectional pin <name> because pin assigned to global clock <name>

Ignored Decrease Input Delay to Internal Cells logic option assignment to input or bidirectional pin <name> because pin assigned to VREF pad <name>

Ignored Decrease Input Delay to Internal Cells logic option assignment to input or bidirectional pin <name> because pin uses input register

Ignored DEDICATED_MULTIPLIER_CIRCUITRY parameter with setting <name> for node <name>

Ignored Design Section -- it is not supported

Ignored Differential setting of Termination logic option setting on pin <name> because pin I/O standard of <name> not supported by differential termination

Ignored don't care value <text> -- value is in Boolean expression that contains comparator

Ignored DSP block balancing assignment <name> for node <name>

Ignored duplicate design unit <name> in file <name>

Ignored duplicate entity <name> found in file <name>

Ignored duplicate Global Signal logic option for I/O cell <name> from signal <name>

Ignored duplicate name

Ignored duplicate of assignment <name> for node <name>

Ignored enable1 port of LVDS receiver <name> because USE_ENABLE1 is set to OFF

Ignored fast fit compilation setting because fast fit compilation is not supported for selected device family

Ignored Fast Input Register logic option assignment for node <name>

Ignored Fast Input Register option on input pin <name> -- can't find valid input register

Ignored Fast Input Register option on input pin <name> -- can't find valid input register

Ignored Fast Input Register option on input pin <name> -- pin is a dedicated input pin or its register is driving global signal

Ignored Fast Input Register option on input pin <name>-- pin is a dedicated input pin

Ignored Fast Input Register option on input pin <name>-- pin is a dedicated input pin

Ignored Fast Input Register option on logic cell <name> that feeds pin <name> -- conflicting assignments

Ignored Fast Input Register option on logic cell <name> that is fed by input pin <name>

Ignored Fast Output Register option on logic cell <name> that feeds pin <name> -- conflicting assignments

Ignored Fast Output Register option on logic cell <name> that feeds pin <name> -- conflicting assignments

Ignored Fast Output Register option on output pin <name> -- can't find a valid output register

Ignored Fast Output Register option on output pin <name> -- can't find a valid output register

Ignored Fast Output Register option on output pin <name> -- pin feeds internal global bus

Ignored Fast Output Register option on output pin <name> -- pin feeds internal global bus

Ignored Fast Output Register or Fast Output Enable Register options on logic cell <name> that feeds output pin <name>

Ignored FastRow interconnect assignment to I/O node <name> -- I/O node <name> fans out to destination nodes assigned to a different Fast Region

Ignored FastRow Interconnect Delay logic option for pin <name> -- pin does not feed the FastRow interconnect

Ignored Global Signal assignment for cell <name>

Ignored Global Signal assignment for I/O cell <name>

Ignored Global Signal logic option assignment for logic cell <name> -- use Assignment Organizer dialog box to select available Global Signal settings

Ignored Global Signal logic option for signal from source cell <name> to destination cell <name> because destination cannot use global signals

Ignored Global Signal logic option for source cell <name> to destination cell <name> because source does not feed directly to destination

Ignored I/O node <name> assignment to the FastRow Interconnect because it is not an input or bidirectional node

Ignored I/O node <name> assignment to the FastRow Interconnect because node does not contain location assignment

Ignored I/O pin <name> assignment to the FastRow Interconnect because I/O pin assignment contains invalid location assignment

Ignored input port coeff_in -- port not supported

Ignored input port sclr -- port not used in current design

Ignored input port select -- port not supported

Ignored input port sload_coeff -- port not supported

Ignored input port sload_data -- port not used in current design

Ignored Input Reference assignment for node <name> -- output pin does not use VREFA/VREFB

Ignored Input Reference logic option for node <name> -- only input/bidirectional pins using voltage-referenced I/O standards require a VREF setting

Ignored location assignment on logic cell <name> that feeds output pin <name>

Ignored location assignment on logic cell <name> that is fed by input pin <name>

Ignored location property <name> -- cannot find a suitable port in the netlist for the project

Ignored Logic Cell Insertion logic option on <name> -- Logic Cell Insertion can only be assigned to non-global direct data path connections

Ignored Logic Cell Insertion logic option on node <name> -- illegal value specified for number of logic cells to insert

Ignored LogicLock and/or custom region assignments on some nodes fed by LVDS transmitter node <name>

Ignored LogicLock region assignments on following nodes in carry or cascade chain beginning on node <name> because of location assignment on node <name>

Ignored LogicLock region or custom region assignments on the following nodes

Ignored LogicLock region or custom region assignments on the following nodes because of carry or cascade chain placement requirements

Ignored LogicLock region or custom region assignments on the following nodes because of Fast Input Register, Fast Output Register, or Fast Output Enable Register assignments

Ignored LogicLock region or custom region assignments on the following nodes because of Fast Input Register, Fast Output Register, or Fast Output Enable Register assignments

Ignored LogicLock region or custom region assignments on the following nodes because of Fast Input Register, Fast Output Register, or Fast Output Enable Register assignments

Ignored LogicLock region or custom region assignments on the following nodes because of pin placement requirements

Ignored LogicLock region or custom region assignments on the following nodes because these nodes belong to a PLL

Ignored LogicLock region or custom region assignments on the following nodes in order to optimize I/O cell register placement for timing

Ignored LogicLock region or custom region assignments on the following nodes, which feed tri-state bus <name>, because of deep RAM placement requirements

Ignored Maximum Fan-Out assignment

Ignored Maximum Fan-Out logic option for <name>

Ignored named operator <name> -- operator is named in arithmetic expression and not in Boolean expression that generates logic

Ignored node <name> assignment to clique <name> of type <name> -- clique type not supported

Ignored node <name> assignment to clique <name> of type <name> -- clique type not supported

Ignored node assignments for some register-node combinations while performing <name> register packing

Ignored node in vector source file. Can't find corresponding node name <name> in design.

Ignored one or more files listed in file <name> because files with the same names were already selected

Ignored one or more illegal reserve pin AS_VREF keywords

Ignored output port load_done -- port not supported

Ignored parameter MAX_CLOCK_CYCLES_PER_RESULT -- parameter not supported

Ignored parameter NUMBER_OF_COEFFICIENTS -- parameter not supported

Ignored parameter WIDTH_S -- parameter not supported

Ignored port <name> in symbol <name> -- port is illegal

Ignored Power-Up High logic option setting for state bit <name> -- using reset state's zero value instead

Ignored Power-Up High option on the following nodes -- nodes are set to power up low

Ignored Power-Up High option on the following nodes -- nodes are set to power up low

Ignored Power-Up High option on the following nodes -- nodes are set to power up low

Ignored Power-Up High option on the following nodes -- nodes are set to power up low

Ignored promotion of peripheral signal for node <name> to an I/O cell signal of type <type> -- not have enough input I/O pins

Ignored promotion of peripheral signal for node <name> to I/O cell signal of type <type> -- not enough peripheral buses

Ignored Regional or Fast Regional Clock setting for node <name> -- Regional and Fast Regional Clock settings are not supported for target device

Ignored Row-Global Signal logic option for node <name>

Ignored SignalProbe assignment -- cannot place pin <name> at pin location <name> in device

Ignored some user assignment because of placement requirements for assigned differential I/O standards

Ignored some user assignments because of placement requirements for assigned I/O standards

Ignored some user assignments because of placement requirements for assigned LVDS standards

Ignored Termination logic option setting <name> assigned to pin <name> because it is illegal

Ignored the following <number> conflicting DSP block balancing assignments or megafunction parameter settings made to DSP block slice with DSP block output node <name>

Ignored the following conflicting DSP block balancing assignments or megafunction parameters in <number> DSP block slices

Ignored title block(s) in Graphic Design File <name>

Ignored Virtual Pin assignment on output enabled pin <name>

Ignored Virtual Pin assignment on registered pin <name>

Ignoring <name> parameter in LVDS transmitter <name> because LVDS transmitter is not in bypass mode

Ignoring assignments for <name>[<number>][<number>] because it is an invalid assignment target -- <name> is a single bit, and cannot have members

Ignoring check outputs option. Can't find vector source file.

Ignoring CLKLOCK primitives with ClockBoost parameter of 1 -- ClockLock PLLs not supported in target device family

Ignoring CLKLOCKx1 Input Frequency logic option -- ClockLock PLLs not supported in target device family

Ignoring Clock Enable Routing option for all nodes

Ignoring corrupt symbol(s) in file <name>

Ignoring external input and/or output delay assignments

Ignoring illegal initialization setting <name> = <name> in the quartus.ini file or ini_vars line in the Compiler Settings File

Ignoring location <name>, assigned to <name>

Ignoring location assignment <name>, assigned to node <name>

Ignoring Multicycle assignment(s). Multicycle assignments can be used only with clock frequency requirements.

Ignoring node <name> global assignment -- node does not have a destination

Ignoring Output Enable Routing option for all nodes

Ignoring output pin <name> in vector source file when writing test bench files

Ignoring preferred location <location> on node <name>

Ignoring preferred location <location> on node <name> because user assignments on the node require it to be placed in the LogicLock region with lower-left corner <location> and upper-right corner <location>

Ignoring property name <name> because it is already defined

Ignoring setting <name> -- value <name> is illegal. Refer to --help for legal values.

Ignoring SignalTap II instance <name> with signal set <name>

Ignoring the following preferred locations

Ignoring unsupported logic options <name>, <name>, or <name> -- turn off logic options

Ignoring user clique <name>, member nodes have conflicting location assignments

Ignoring Virtual Pin assignment made to bidirectional pin <name>

Ignoring Virtual Pin assignment to node <name>

Ignoring Virtual Pin assignment(s) -- current device does not support Virtual Pin assignment

Illegal asynchronous reset at time <time> on address input register of memory segment <name>

Illegal asynchronous reset at time <time> on address input register of memory segment <name>

Illegal asynchronous reset at time <time> on data input register of memory segment <name>

Illegal asynchronous reset at time <time> on read enable register of memory segment <name>

Illegal asynchronous reset at time <time> on write enable register of memory segment <name>

Illegal bus range or name for logic function for instance <name> of type <type>

Illegal character <text> in port inversion pattern -- character must be hexedecimal

Illegal connection dot -- junction placed incorrectly

Illegal custom region <name>-- coordinates of region are inconsistent

Illegal database file name <name> -- file name is too long

Illegal default value on pin <name>

Illegal destination <name>

Illegal differential I/O standard assigned to pins of PLL <name>

Illegal DQS Frequency setting <name> for DQS I/O pin <name>

Illegal EDA <name> tool name <name>

Illegal ERROR_CHECK_FREQUENCY_DIVISOR value in Compiler Settings File

Illegal expression

Illegal frequency <number> MHz for INPUT_FREQUENCY parameter for Clocklock PLL <name> -- frequency must be between <number> and <number> MHz

Illegal instance name

Illegal instance name -- enter a legal instance name

Illegal location used to define custom region

Illegal location used to define LogicLock region

Illegal mode value for M counter of PLL <name> -- set M modulus to 1

Illegal mode value for N counter of PLL <name> -- set N modulus to 1

Illegal multidimensional bus

Illegal name <name> -- pin name already exists

Illegal output file name

Illegal pin assignment -- node <name> is assigned to <name>, which is needed for automatic or individual global clock signals in your design

Illegal pin assignment -- node <name> is assigned to <name>, which is needed for automatic or individual global clear signals in the design

Illegal pin assignment -- node <name> is assigned to pin <name>, which is needed for automatic or individual global output enable signals in your design

Illegal pins in Verilog HDL

Illegal port connection -- input port <name> of GXB receiver channel atom <name> cannot be connected because <text> is not allowed

Illegal port connection -- input port <name> of GXB transmitter channel atom <name> cannot be connected because <text>

Illegal port connection -- input port <name>[<number>] of GXB receiver channel atom <name> is connected

Illegal port connection -- output port <name> of GXB receiver channel atom <name> cannot be connected because <text> is not allowed

Illegal port connection -- port <name> of XGMII state machine atom <name> cannot be connected

Illegal port name: <name>

Illegal SignalProbe source <name>

Illegal size for LogicLock region <name> -- LogicLock regions for the current device cannot extend onto pins

Illegal size for LogicLock region <name> -- size would make region exceed bounds of its parent LogicLock region

Illegal size for LogicLock region <name> -- size would make region exceed bounds of target device

Illegal size for LogicLock region <name> -- size would make region too small to contain its back-annotated nodes

Illegal size for LogicLock region <name> -- size would make region too small to contain its child LogicLock regions

Illegal value in compiler setting <name> changed to family default value <name>

Illegal value or string encountered while parsing Conversion Setup File

Illegal wire or bus name <name> of type <type>

Illegal zero value for M counter of PLL <name> in non-bypass mode -- set M modulus to 1

Illegal zero value for N counter of PLL <name> in non-bypass mode -- set N modulus to 1

Implemented <name> for PLL <name>

Implemented <number> bidirectional pins

Implemented <number> ClockLock PLLs

Implemented <number> content-addressable memory segments

Implemented <number> device resources

Implemented <number> DSP elements

Implemented <number> dual-port RAM elements in Excalibur device

Implemented <number> input pins

Implemented <number> logic cells

Implemented <number> macrocells

Implemented <number> microprocessor core elements in Excalibur device

Implemented <number> output pins

Implemented <number> RAM segments

Implemented <number> shareable expanders

Implemented <number> tri-state elements

Implemented clock multiplication and clock division parameter values, but can't implement phase shift parameter values for PLL <name>

Implemented pre-divider for cruclk input frequency <number> of GXB receiver channel atom <name>

Implementing clock multiplication and clock division parameter values for PLL <name>

Implementing clock multiplication of <number>, clock division of <number>, and phase shift of <number> degrees (<number> ps) for <name> port

Implementing hierarchy <name> using look-up table logic

Implementing hierarchy <name> using product term logic

Implementing parameter values for PLL <name>

Implementing parameter values for PLL <name>

Implementing value for PHASE_SHIFT = <number> ps

Implementing value for PHASE_SHIFT = <number> ps

In altmult_add megafunction, NUMBER_OF_MULTIPLIERS parameter setting is <number>, but altmult_add megafunction cannot use scanouta or scanoutb when value of NUMBER_OF_MULTIPLIERS parameter is 3

In altmult_add megafunction, NUMBER_OF_MULTIPLIERS parameter setting is <number>, but value of NUMBER_OF_MULTIPLIERS parameter must be less than or equal to 4

In current operating mode, WYSIWYG RAM primitive <name> cannot have <name> port or parameter connected

In current operating mode, WYSIWYG RAM primitive <name> cannot have <name> port or parameter connected

In FLEX 6000 devices, regout port and combout port cannot be connected at same time in LCELL atom <name>

In multiplier mode, ATOM <name> cannot use aload port

In multiplier mode, ATOM <name> cannot use datac port

In multiplier mode, ATOM <name> cannot use datad port

In multiplier mode, ATOM <name> has illegal outputs

In multiplier mode, ATOM <name> must connect its multout or regout port to dataa or datab port of only one other ATOM

In multiplier mode, ATOM <name> must use dataa port if multsela and multselb ports use the dataa port

In multiplier mode, ATOM <name> must use datab port if multsela and multselb ports use the datab port

In multiplier mode, ATOM <name> must use multout, combout, or regout port

In multiplier mode, ATOM <name> must use multsela port

In multiplier mode, ATOM <name> must use multselb port

In single-port mode, ATOM <name> cannot have different raddr and waddr ports

In single-port mode, WYSIWYG RAM primitive <name> cannot have different raddr and waddr ports

In the current operating mode, WYSIWYG RAM primitive <name> cannot have <name> port or parameter specified on port B

In the current operating mode, WYSIWYG RAM primitive <name> cannot have <name> port or parameter specified on port B

inclk and outclk ports must have same source when DDIO_MODE parameter is set to INPUT for I/O ATOM <name>

inclk<0 or 1> input frequency of <number> for <type> PLL <name> must be in the frequency range of <number> to <number>

inclk0 and inclk1 of enhanced PLL <name> cannot be fed by the same source

inclk0 input frequency <number> for GXB receiver PLL of GXB receiver channel atom <name> must be in frequency range <number> to <number>

inclk0 input frequency of <number> for <Text> PLL must be in the frequency range of <number> to <number> for a multiplication factor of <number>

inclk0 port of PLL <name> must be driven by a non-inverted input pin or, in a fast PLL, the output of a PLL

inclk1 port of enhanced PLL <name> must be driven by a non-inverted input pin

INCLOCK_BOOST parameter of HSDI PLL ATOM <name> has value of <number>, but value must be 1-12, 14, 16, 18, or 20

Include file generation was <successful, NOT successful, stopped, or canceled due to an error>

INCLUDE keyword in Include Statement must be followed by a file name enclosed in quotation marks (")

Include Statements in Text Design File cannot include file <name> more than once

Incorrect connector style at port <name> for symbol <name> of type <name>

Incremental compilation for preferred locations can't place node <name>

Incremental compilation for preferred locations can't place the following nodes

Incremental compilation is in progress

Incremental compilation is in progress

Incremental Synthesis wrote following Memory Initialization Files to directory <name>

Incrementally routed pre-synthesis source node <name>

Index of location <name> must be <name> <number>

Index of pad assignment <name> must be between 1 and <number>

Individual pin I/O standard setting <name> for pin <name> not supported for selected device family

Individual pin I/O standard setting <name> for pin <name> not supported for selected migration device family

Information required for future SignalProbe compilations will not be saved

Information required for future SignalProbe compilations will not be saved -- netlist contains duplicate signal names

Initial placement failed after <number> attempts. LogicLock region <name> had the largest number of placement failures.

Initialization data at line number <number> in Hexadecimal (Intel-Format) File <name> cannot be read because <text>

Initialization data in Hexadecimal (Intel-Format) File for memory region at address [0x<number>, 0x<number>] cannot be used because region is part of programmable logic device memory region of ARM-based Excalibur device

Initialization data in Hexadecimal (Intel-Format) File for memory regions at address [0x<number>, 0x<number>] and [0x<number>, 0x<number>] cannot be used because the memory regions overlap

Initialization data in Hexadecimal (Intel-Format) File(s) cannot be used for memory region at address [0x<number>, 0x<number>] because memory region is not mapped

Initialized simulation successfully. Do you want to run the simulation?

Initiated remote configuration of remote update block at time <time>

Input <name> of LVDS receiver <name> does not feed the receiver directly because <text>

Input <name> of the <name> <name> cannot be connected to VCC or GND

Input <name> of the <name> <name> cannot be connected to VCC or GND

Input <type> is empty

Input clock frequency of <number> for ClockLock PLL <name> is greater than maximum operational frequency for <name> I/O standard or internal clock network assigned to <number> for external feedback input pin <name>

Input clock frequency of <number> specified for ClockLock PLL <name> must be within valid range of minimum frequency of <number> to maximum frequency of <number> for CLOCK<1 or 2>_BOOST parameter value of <number>

Input clock frequency specified of <number> for ClockLock PLL <name> must be within valid range of minimum frequency of <number> to maximum frequency of <number> for CLOCK<1 or 2>_BOOST parameter value of <number>

Input clock of LVDS receiver <name> must be fed by an LVDS receiver PLL

Input clock of LVDS transmitter <name> must be fed by an LVDS transmitter PLL

Input clock pin <name> is assigned to an I/O pin that feeds input clock of ClockLock PLL <name>, which uses clock output port <clk0 or clk1> to feed other clock ports in design. Input clock pin <name> must not clock other logic.

Input clock pin <name> is assigned to an I/O pin that feeds input clock of ClockLock PLL <name>, which uses output clock ports clk0 and clk1 to feed other clock ports in design. Therefore, input clock pin <name> cannot clock other logic.

Input clocks and output clocks of enhanced PLL <name> require <number> global clocks but the PLL cannot use more than <number> global clocks

Input frequency of <number> for ClockLock PLL <name> is greater than maximum operational frequency of <number> for <name> I/O standard or internal clock network assigned to clock input pin <name>

Input frequency of <number> for HSDI PLL <name> must be in the frequency range of <number> to <number> for an HSDI multiplication factor of <number>

Input frequency of enhanced or fast PLL <name> must be in the frequency range of <number> Mhz to <number> Mhz for locking

Input I/O cell <name> has 3.3-V PCML I/O standard, but is assigned to a pin that does not support this differential I/O standard

Input I/O cell <name> has differential I/O standards, but is assigned to a pin that cannot be used as differential input

Input node <name>, which is assigned to LVDS transmitter clock input pin <name>, feeds LVDS transmitter PLL <name> clock input port, but also feeds other destinations

Input pin <name> cannot be assigned a value

Input pin <name> cannot feed more than datain port of GXB receiver channel <name> and serialdatain port of GXB transmitter channel

Input pin <name> drives <number> SERDES receivers, but must drive only one SERDES receiver

Input pin <name> feeds <inclk0 or inclk1> of enhanced PLL <name> and the inclk port of a fast PLL -- routing inclk0 port of the fast PLL via global clocks

Input pin <name> feeds <number> ClockLock PLLs but can only feed <number> ClockLock PLLs

Input pin <name> feeds <type> of enhanced PLL <name> and inclk port of another enhanced PLL, but input pin <name> cannot feed inclk port of another enhanced PLL

Input pin <name> feeds clock enable port of ClockLock PLL <name>, but also feeds other logic

Input pin <name> feeds ena input port of enhanced or fast PLL <name> and other logic -- input pin <name> should not feed other logic

Input pin <name> feeds inclk ports of <number> enhanced PLLs -- the input pin cannot feed inclk ports of more than <number> enhanced PLLs

Input pin <name> feeds inclk0 port of <number> fast PLLs -- some inclk0 ports will be routed via global clocks, which may reduce performance

Input pin <name> feeds pllenable input port of XGMII state machine atom <name> and other logic, but input pin <name> can't feed other logic

Input pin <name> feeds the fbin input port of enhanced PLL <name> and other logic

Input pin <name> of port <type> can feed only ClockLock PLL <name> because ClockLock PLL input pin <name> is user-assigned to <name>

Input pin <name>, which feeds fbin port of enhanced PLL <name>, and output pin <name>, which will be compensated by PLL <name>, have different I/O standards <name> and <name>

input port <name> cannot be assigned a value

Input port <name> of GXB receiver channel atom <name> cannot be connected because <text>

Input port <name> of GXB receiver channel atom <name> cannot be connected when GXB receiver channel atom <name> is not in 8B/10B mode

Input port <name> of GXB receiver channel atom <name> cannot be connected when GXB receiver channel atom <name> is not in channel alignment mode

Input port <name> of GXB receiver channel atom <name> has width <number>, but must have width <number>

Input port <name> of GXB receiver channel atom <name> is connected, but this connection is not allowed because <text>

Input port <name> of GXB receiver channel atom <name> must be connected

Input port <name> of GXB receiver channel atom <name> must be connected because <text>

Input port <name> of GXB receiver channel atom <name> must be fed by output port <name> of GXB transmitter PLL

Input port <name> of GXB receiver channel atom <name> must be fed by output port <name> of GXB transmitter PLL because <text>

Input port <name> of GXB receiver channel atom <name> must be fed only by output port <name> of a GXB receiver channel atom in channel 0

Input port <name> of GXB receiver channel atom <name> must connect to output port <name> of an XGMII state machine atom

Input port <name> of GXB receiver channel atom <name> must connect to output port <name>[<number>] of an XGMII state machine atom

Input port <name> of GXB transmitter channel atom <name> must be fed by an input pin

input port <name> of GXB transmitter channel atom <name> must be fed by CLK<number> port of GXB transmitter PLL

Input port <name> of GXB transmitter channel atom <name> must connect to output port <name> of a GXB receiver channel atom when in reverse parallel loopback mode

Input port <name> of GXB transmitter channel atom <name> must connect to output port <name>[<number>] of an XGMII state machine atom

Input port <name> of SignalTap II Logic Analyzer can be fed only by a dedicated pin

Input port <name> of the <name> <name> is missing source

Input port <name> of XGMII state machine atom <name> must be connected only to an input pin

Input port <name> of XGMII state machine atom <name> must be fed by CLK<number> of GXB transmitter PLL

Input port <name> of XGMII state machine atom <name> must connect to output port <name> of atom <name> in channel 0

Input port <name>.<name> cannot be used as a value

Input port <name>[<number>] of GXB receiver channel atom <name> is connected -- this connection is not supported because <text>

Input port <name>[<number>] of GXB receiver channel atom <name> is unconnected -- this is not supported because <text>

Input port <name>[<number>] of GXB receiver channel atom <name> must connect to output port <name>[<number>] of a GXB transmitter channel atom in the same channel

Input port <name>[<number>] of XGMII state machine atom <name> must connect to output port <name> of atom <name> in channel <number>

Input port <name>[<number>] of XGMII state machine atom <name> must connect to output port <name>[<number>] of atom <name> in channel <number>

Input port of LVDS transmitter <name> should not be inverted

Input port other than cin or cascin of LCELL ATOM <name> is fed by another LCELL ATOM's cout or cascout port

Input port other than cin or cascin of WYSIWYG LCELL primitive <name> is fed by another WYSIWYG LCELL primitive's cout or cascout port

Input port(s) of LVDS receiver <name> must be connected directly to input I/O nodes in the design

Input ports of HSDI receiver <name> must be connected directly to input pins

Input reference <name> is enabled, but not used

Input registers in I/O cell <name> will power up low

Input signal of LVDS transmitter <name> should not be inverted

Input signals of LVDS transmitter <name> are not fed by a register

Input signals of LVDS transmitter <name> should be connected to a register

INPUTC, OUTPUTC and BIDIRC pins not supported for pin <name>

Inserted <number> logic cells after node <name>

Inserted <number> logic cells between source node <name> and destination node <name>

Inserted <number> logic cells for Maximum Fan-Out assignment on <name>

Inserted <number> logic cells in first fitting attempt

Inserted <number> logic cells in the output data path <name> of SERDES receiver <name>

Inserted logic cell <name> assigned to location <name>

Inserted logic cells in the output data path <name> of SERDES receiver

Inserting extra timing delay for MultiVolt IO interface

Instance name already exists

Instance name already exists in current Block Design File -- enter a unique instance name

Insufficient I/O pins in selected migration devices to support device migration

Insufficient room to paste memory cell values

Intermediate files purge was <successful, NOT successful, stopped, or canceled due to an error>

Invalid JTAG configuration

Invalid port name <name>

Invalid SignalProbe output pin <name> -- device output pin could not be found

Invalid SignalProbe source <name> -- SignalProbe source could not be found or is an unsupported type

Invalid SignalProbe source node <name> -- SignalProbe source signal could not be found or is of an unsupported type

Iterator variable has name <name>, but name is already used as a constant, parameter, or node name

J

Jam File or Jam Byte-Code File must have cyclic redundancy check code

Jam File, Jam Byte-Code File, Serial Vector Format File, or In System Configuration File <name> already exists. Do you want to overwrite file?

Jam File, Jam Byte-Code File, Serial Vector Format File, or In System Configuration File <name> does not contain valid path name

Jam File, Jam Byte-Code File, Serial Vector Format File, or In System Configuration File <name> is read-only. Select another file name.

Jam File, Jam Byte-Code File, SRAM Object File, or Programmer Object File contains cyclic redundancy check code <number> that does not match expected CRC code <number>. Do you want to ignore CRC code and add file to JTAG chain?

Jam Files, Jam Byte-Code Files, Serial Vector Format Files, and In System Configuration Files do not support EPC16 configuration device

JTAG block <name> does not support input port <name>

JTAG communication error

JTAG communication error -- use the current SRAM Object File and check the hardware setup

JTAG ID code specified in Jam File does not match any valid JTAG ID codes for device

JTAG pin <name> can be assigned only to location <name>

JTAG port <name> must connect to an I/O pin

JTAG port <name> must connect to I/O pin

JTAG ready

JTAG Server can't access selected programming hardware

JTAG server is not responding

JTAG Server not running. Switching to hardware dll.

JTAG Server out of memory

JTAG standard requires odd value for JTAG ID and JTAG ID mask

JTAG support disabled in file <name>

JTAG user code in Slave Binary Image File <name> must correspond to a valid ARM-based Excalibur device

JTAG user code must be a hexadecimal number of 32 bits or less

K

Keyword <name> in settings and configuration file <name> is not a legal keyword of section <name> -- deleting illegal keyword

L

Lab clique <name> requires <number> programmable interconnect arrays (PIA), but clique can contain only <number> PIAs

LAB index of location <name> should be <name> <number>

Latch <number> contains <number> node(s)

LATCH primitive <name> is permanently disabled

LATCH primitive <name> is permanently enabled

LCELL atom <name> cannot feed more than one regcascin port

LCELL ATOM <name> cannot use datad port when in arithmetic or counter mode

LCELL ATOM <name> cannot use regcascin port that uses illegal port

LCELL ATOM <name> fans out via carry or cascade chains to more than one destination LCELL ATOM

LCELL ATOM <name> has a cout or cascout port that feeds another LCELL ATOM's input port other than cin or cascin port

LCELL ATOM <name> has a cout port that feeds another LCELL ATOM's input port that is not a cin port

LCELL ATOM <name> has a cout port that feeds more than one input port, but LCELL ATOM must feed only one input port

LCELL ATOM <name> has an inverta port connection, but is not part of a carry chain

LCELL ATOM <name> has cin and cascin ports that are connected to different LCELL ATOMs, but the ports must be connected to the same LCELL ATOM's cout and cascout ports

LCELL atom <name> has combout port that feeds clock signal input port of another atom

LCELL atom <name> has regout port that feeds clock signal input port of another atom

LCELL ATOM <name> is dependent on unconnected input ports

LCELL ATOM <name> must use asynchronous data port if aload port is used

LCELL atom <name> must use clk port when in QFBK mode

LCELL atom <name> must use clk port when using regout port

LCELL ATOM <name> must use its datac port when sload port is connected

LCELL ATOM <name> must use synchronous data port if sload port is used

LCELL ATOM <name> must use the datac port when aload port is connected

LCELL ATOM <name> uses aclr port, but does not use regout port

LCELL ATOM <name> uses aload port, but does not use its regout port

LCELL ATOM <name> uses illegal cout port with fan-out when in normal mode

LCELL ATOM <name> uses improperly connected cascin port

LCELL ATOM <name> uses improperly connected cin port

LCELL ATOM <name> uses inconsistent inverta port connections

LCELL ATOM <name> uses its apre port, but does not use its regout port

LCELL ATOM <name> uses its clk port, but does not use its regout port

LCELL ATOM <name> uses its ena port, but does not use its regout port

LCELL ATOM <name> uses its sclr port, but does not use its regout port

LCELL ATOM <name> uses its sload port, but does not use its regout port

Left of Boolean equation cannot contain text <text>

LeonardoSpectrum software error: <text>

LeonardoSpectrum software information: <text>

LeonardoSpectrum software warning: <text>

Library Mapping File <name> contains one or more syntax errors

Library Mapping File <name> contains one ore more syntax errors

License file <name> does not exist. Compilation and simulation support is not available until or unless you specify a valid license file.

License file does not contain information required to run the Quartus II software. You must obtain a valid license file with permission to run the Quartus II software.

License file has expired -- compilation and simulation support is not available until you specify a valid license file

License file is not specified -- compilation and simulation support is not available until you specify a valid license file

License file settings changed. Restart the Quartus II software for the changes to take effect.

License for core <name>, version <version> is expired

Limited to <number> non-global destinations

Line <number> in Cross-Reference File <name> contains a syntax error

Line <number> in Cross-Reference File <name> contains illegal tool or vendor <name> instead of tool or vendor <name>

Line <number> in Cross-Reference File <name> is missing double quotes

Line <number> of Chain Description File <name> contains syntax error

Line <number> of Cross-Reference File <name> contains a duplicate design name, which is illegal

Line <number> of Cross-Reference File <name> contains an instance that is used more than once, but the line is missing a "+" at its end

Line <number> of Cross-Reference File <name> contains an unexpected end of line

Line <number> of Cross-Reference File <name> contains duplicate statement, which is illegal

Line '<text>' at line number <number> in data file <name> is not valid

Linker is linking boot data file with bootloader library file to generate Executable and Linkable Format File

Linker is linking object files to generate Executable and Linkable Format File

List of <number> logic cells constrained to a LAB

List of logic cells in the chain (ordered from chain start to end)

List of logic cells in the clique

List of nodes moved into LogicLock region <name> for chain beginning on node <name>

List of states in WHEN clause of state machine Case Statement cannot be enclosed in parentheses

Listing peripherals in Slave Binary Image File <name>

LMF mapping record <name> -> <name> missing the <name> port mapping(s) for node <name>

Loc. = <location name>; Node <name>

Location <name> has correct location type, but location type has incorrect syntax

Location <name> is assigned to <name>

Location <name> is not a legal origin for LogicLock region <name>

Location <name> is not supported on the current device

Location <name> must contain valid location type

Location <number> of dual-port RAM ADDRESS_WIDTH <number> and DATA_WIDTH <number> is illegal -- must be within legal range of 0 to <number>

Location assignment for <name> I/O pin <name> is illegal -- location must be a <name> I/O pin in device

Location assignment for DQS I/O pin <name> places it in a location or region on device that cannot accommodate the DQS I/O pin and DQ I/O pins driven by it

Location assignment for nodes in LAB <name> contains <number> programmable interconnect arrays (PIA), but the LAB cannot contain more than <number> PIAs

Location assignments cannot be edited while viewing results of the last compilation. Switch to current assignments?

Location with name <name> in device <name> already exists

LOCK pin cannot be assigned LVDS or LVPECL I/O standards

Lock range from <number> to <number> -- cannot lock enhanced or fast PLL

Locked output of a ClockLock PLL must drive (positively) only one output pin, the locked pin

Logic between pin <name> and its register contains a loop -- can't implement Power-Up High option

Logic cell <name>

Logic cell <name> cannot use non-global clock, non-global clock enable, non-global clear, and non-global preset/aload simultaneously

Logic cell <name> cannot use non-global synchronous clear (<name>), non-global synchronous load (<name>), and non-global clear (<name>) simultaneously

Logic cell <name> is assigned to location <name>

Logic cell <name> requires <number> non-global secondary signals, but the selected device allows only <number> signals

Logic cell <name> requires <number> resources from the Programmable Interconnect Array (PIA), but the PIA can contain only <number> resources

Logic cell <name> requires <number> secondary signals of types <type>, <type>, <type>, <type>, and <type>, but the selected device allows only <number> signals

Logic cell <name> requires <number> shareable expanders, but the device can contain only <number> shareable expanders

Logic cell <name> will power up low

Logic cell <name> will power-up low

Logic cell <number>: <name>

Logic cell assigned to location <name>

Logic function of type <name> and instance <name> is already defined as a signal name or another logic function

Logic level <number or text> does not match expected logic level <number or text> for node <name> at time <time>

Logic level <number or text> does not match expected logic level <number or text> for node <name> at time <time>

Logic level at time <time> on read enable of memory segment <name> is illegal

Logic level at time <time> on write enable of memory segment <name> is illegal

Logic level(s) do not match expected level(s)

Logic level(s) do not match expected level(s)

Logic option setting <name> of PLL <name> is different from setting for DQS I/O pins driven by PLL

Logical RAM <name> and logical RAM <name> use the same logical RAM name <name>

LogicLock region <name>

LogicLock region <name> assigned to parent LogicLock region <name>, but this parent LogicLock region does not exist in the project

LogicLock region <name> at origin <location> has illegal height <number>

LogicLock region <name> at origin <location> has illegal width <number>

LogicLock region <name> contains illegal setting <number or text> for keyword <text>

LogicLock region <name> does not have height or width

LogicLock region <name> exceeds bounds of parent LogicLock region <name>

LogicLock region <name> has <text>

LogicLock region <name> has a locked location but no origin

LogicLock region <name> has circular hierarchy

LogicLock region <name> has illegal origin <location>

LogicLock region <name> has illegal origin <location>

LogicLock region <name> has illegal origin <location>

LogicLock region <name> has locked location but its parent LogicLock region <name> has no origin

LogicLock region <name> has Reserved unused logic cells turned on -- ignored soft property for this region

Logiclock Region <name> has Soft property turned on -- ignored back-annotated node locations in this region

Logiclock Region <name> has Soft property turned on -- ignored locked locations of child LogicLock regions

LogicLock region <name> is <auto-size or floating>, but Mercury devices support only fixed-size, locked LogicLock regions

LogicLock region <name> with top left corner of <location> and bottom right corner of <location>

LogicLock region name: <name>

Looking for devices

Low-level port(s) or multiple ports cannot be connected to padio of WYSIWYG primitive

lpm_rom <text> must have a Memory Initialization File or Hexadecimal (Intel-format) File with matching name in project directory

LUT_MASK value <number> must be four-digit hexadecimal number

LVDS input node <name> cannot route to LVDS receiver node <name> because they have conflicting assignments

LVDS receiver <name>'s clock0 and clock1 input ports must be fed by the same LVDS receiver PLL

LVDS receiver <name>, which you assigned to location <name>, cannot have its LVDS input node <name> placed at location <name> because that location is already occupied by node <name>

LVDS receiver input skew margin for data pin <name>, LVDS receiver channel <name>, and clock <name> is <time>

LVDS receiver input skew margin is negative <number> on data pin <name>. LVDS circuit may not operate.

LVDS Receiver PLL <name> cds_ena signal de-asserted too early at <time>

LVDS Receiver PLL <name> rx_deskew signal de-asserted too early at <time>

LVDS sampling window size is <time>

LVDS time unit interval is <time>

LVDS transmitter <name>, which you assigned to location <name>, cannot have its LVDS output node <name> placed at location <name> because that location is already occupied by node <name>

LVDS transmitter channel-to-channel skew for data out port <name>, LVDS transmitter channel <name>, and clock out port <name> is <time>

LVDS transmitter channel-to-channel skew is <time>

LVDS transmitter clock input pin <name> requires dedicated clock pin, but all dedicated clock pins are used

M

Macrocell <name> assigned to <name> in Compiler Setting File drives a pin, but the pin already drives a JTAG pin

Macrocell <name> assigned to <name> in Compiler Setting File drives a VREFA pin, but you cannot assign a non-buried macrocell driving a VREFA pin

Macrocell <name> assigned to <name> in Compiler Setting File drives a VREFB pin, but you cannot assign a non-buried macrocell driving a VREFB pin

Macrocell <name> assigned to <name> in Compiler Setting File is a buried macrocell, but you cannot assign a pin/non-buried macrocell to a buried macrocell

Macrocell buffer inserted after node <name>

MainWin license not available -- compilation and simulation support is not available until you specify a valid license file

masterclk input port of GXB receiver channel atom <name> must be fed by the recovclkout output port of a GXB receiver channel atom in channel 0

Maximum of two groups allowed for DQS and DQ I/O pins driven by different clocks

Megafunction or macrofunction name <name> cannot be used as an instance name for the logic function

memimagedecoder utility cannot interpret boot data in boot data file

memimagedecoder utility cannot read boot data file <name>

memimagedecoder utility cannot read SRAM Object File

Memory block <name> cannot be assigned to a location of type <type>

Memory block <name> type <type> cannot be assigned to location of memory block type <type>

Memory block size configuration of <number> by <number> for byte enable port does not support port <name>

Memory block type <name> does not support a Memory Initialization File

Memory block type <type> does not support operation mode <name>

Memory block type <type> does not support operation mode <name>

Memory block type <type> does not support parameter <name>

Memory block type <type> does not support parameter <name> in operation mode <name>

Memory block type <type> does not support parameter(s) <name>

Memory block type <type> does not support port <name> and/or port <name>

Memory block type <type> does not support port <name> in operating mode <name>

Memory block type <type> does not support port <name> in operation mode <name>

Memory cell cannot be empty

Memory data generated during simulation is different from actual embedded memory contents. Do you want to refresh embedded memory contents?

Memory declaration error: attribute <name> has illegal value <text>

Memory declaration error: attribute <name> is illegal

Memory declaration error: function must have attribute <name>

Memory declaration error: group declarations are not supported

Memory declaration error: number of segments declared (<number>) must equal number of segments expected (<number>)

Memory declaration error: SEGMENTSIZE <number> is too large (maximum size is <number>)

Memory declaration error: SEGMENTSIZE <number> must be a power of 2

Memory declaration warning: ignored duplicates of attribute <name> -- recognized only last use of attribute

Memory depth value (<number>) in design file differs from memory depth value (<number>) in Memory Initialization File -- setting initial value for remaining addresses to 0

Memory depth value (<number>) in design file differs from memory depth value (<number>) in Memory Initialization File -- setting initial value for remaining addresses to never match

Memory depth value (<number>) in design file differs from memory depth value (<number>) in Memory Initialization File -- truncated remaining initial content value to fit content-addressable memory

Memory depth value (<number>) in design file differs from memory depth value (<number>) in Memory Initialization File -- truncated remaining initial content value to fit RAM

Memory Editor contents have changed. Do you want to update embedded memory contents?

Memory Initialization File <name> contains illegal address radix at line <number>

Memory Initialization File <name> contains illegal depth value at line <number>

Memory Initialization File <name> contains illegal memory radix at line <number>

Memory Initialization File <name> contains illegal width value at line <number>

Memory Initialization File or Hexadecimal (Intel-Format) File <name> contains don't care values -- overwriting them with 0s

Memory Initialization File or Hexadecimal (Intel-Format) File <name> contains illegal syntax at line <number>

Memory Initialization File or Hexadecimal (Intel-Format) File for RAM is not specified -- setting initial contents to 0

Memory Map File <name> contains memory usage information for file <name>

Memory value <number> must be of radix <type>

Memory width value (<number>) in design file differs from memory width value (<number>) in Memory Initialization File -- setting initial value for remaining bits to 0

Memory width value (<number>) in design file differs from memory width value (<number>) in Memory Initialization File -- setting initial value for remaining bits to don't care

Memory width value (<number>) in design file differs from memory width value (<number>) in Memory Initialization File -- truncated remaining initial content value to fit content-addressable memory

Memory width value (<number>) in design file differs from memory width value (<number>) in Memory Initialization File -- truncated remaining initial content value to fit RAM

Memory word <number> is too long

Memory word size must not exceed <number>

Merging clique <name> and clique <name> -- both contain node <name>

Merging clique <name> and clique <name> -- both contain node <name>

Message variable in Assert Statement must be constant, parameter, or arithmetic expression

Messages generated during save -- see messages in the System tab of the Messages window

Minimum frequency <number> is greater than maximum frequency <number> -- cannot lock enhanced or fast PLL <name> when minimum frequency range is greater than maximum frequency range

Minimum pulse width minimum slack time is <time> between clock <name> and destination register <name>

Minimum slack time is <time> between source <pin or register> <name> and destination <pin or register> <name>

Minimum slack time is <time> for clock <name> between source <pin or register> <name> and asynchronous destination memory <name>

Minimum slack time is <time> for clock <name> between source <pin or register> <name> and destination <pin or register> <name>

Missing height or width for <locked, floating, or auto-sized> LogicLock region <name>

Mnemonic entry must contain a value

Mnemonic table <name> does not exist in SignalTap II File

Mnemonic table entry must contain mnemonic name

Mnemonic table must have a name

ModelSim software error: <text>

ModelSim software information: <text>

ModelSim software warning: <text>

Modification to SignalTap II File cannot be undone. Do you still want to continue?

Modified LogicLock region assignments on the following nodes -- nodes belong to a carry chain

Modified LogicLock region assignments on the following nodes -- nodes belong to a cascade chain

Modified LogicLock region assignments on the following nodes -- nodes belong to a DSP block slice

Module blocks that define Excalibur embedded processor stripe in System Build Descriptor File cannot be used because <text>

Module Declaration error: Module Declaration for module <name> cannot contain different ranges for port <name>

Module Instantiation error: Defparam Statement must immediately follow name of its corresponding module

Module Instantiation error: port <name> is in the named port connection list of a Module Instantiation, but the port is not defined in the Module Declaration for instantiated module <name>

Moved origin of new LogicLock region to nearest LAB or ESB location

Moving assignment <name> of non-migratable pin <name> to region Anywhere on Device in Regions window

Moving assignments of non-migratable pins to region Anywhere on Device in Regions window

Multicycle <setup or hold> factor for <source or destination> register is <number>

Multidevice partitioning is not supported in this version of the Quartus II software

Multiple devices in adapter

Multiple files specified in Programmer

Multiple Global Signal logic option settings assigned to logic cell -- can't support all combinations

N

Name <name> contains Verilog HDL keyword

Name <name> contains VHDL keyword

Name <name> in design file <name> contains illegal character for VHDL

Name <name> used for more than one Boolean expression operator or comparator in Text Design File -- ignored all but first use of name

Name <name> used in arithmetic expression must be evaluated function or constant

Name missing for connector connecting to port <name> of type <name> of instance <name>

Name substitution feature used in Function Prototype Statement, Variable Section, or in-line logic function reference, but not enabled in Options Statement

NcSim software error: <text>

NcSim software information: <text>

NcSim software warning: <text>

Neither clock0 port nor clock1 port of <ClockLock PLL> <name> feeds an output pin, but ClockLock PLL is using the fbin port

Net <name> cannot be assigned more than one value

Net <name> cannot be assigned more than one value

Net <name> connects a bidirectional port <name> to an input or output pin

Net <name> contains multiple sources with at least one top-level pin but no destination port

Net <name> has multiple sources, but net should have only one source

Net <name> has no sources. Ignoring net during synthesis.

Net is fed by <name>

Net name <name> is used multiple times, but should be used only once

Netlist contains duplicate signal names -- can't perform SignalProbe compilation following smart compilation

Netlist extraction and synthesis process were <successful, NOT successful, stopped, or canceled due to an error>

New counter <text> of PLL <name> high is <value>

New counter <text> of PLL <name> low is <value>

New counter <text> of PLL <name> mode is <value>

New counter <text> of PLL <name> time delay is <value>

New M counter modulus of PLL <name> is <value>

New M counter time delay of PLL <name> is <value>

New N counter modulus of PLL <name>is <number>

New N counter time delay of PLL <name> is <value>

New word size must be greater than zero

No clock transition on <name> register

No compiler settings found in project that match Partial SRAM Object File <file name>

No device chain in Programmer window

No device is selected

No devices detected

No devices installed

No DQ I/O pins are clocked by DQS I/O pin <name>

No external delays are specified -- assuming zero delay between external registers and pins

No file name or illegal path specified for Verilog Quartus Mapping File -- can't save incremental synthesis results

No file name specified for Conversion Setup File

No global signals are available

No insertion point specified for file

No location was specified for the SignalTap II incremental routing output node <name>. Pin <name> will be used.

No location was specified for the SignalTap II incremental routing output node <name>. Pin <name> will be used.

No LVDS transmitter channel-to-channel skew data exists for data out port <name>, LVDS transmitter channel <name>, and clock out port <name>

No memory devices exist in simulation

No new updates are available on the Quartus II support web site at this time

No new updates are available on the Quartus II support web site at this time

No output dependent on input pin <name>

No output or bidirectional pins in design

No power estimation end time specified -- Used simulation end time

No processed data to purge

No programming file specified for Jam File, Jam Byte-Code File, Serial Vector Format File, or In System Configuration File

No SignalProbe signals compiled -- all are disabled. All SignalProbe pins remain reserved.

No software build settings found in project that match Hexadecimal (Intel-Format) File <file name>

No superset bus at connection

No System Build Description File is available. Programming files may still be produced, but contain no register settings and user data. No simulator initialization file will be produced.

No unit of measure specified for frequency of DQS I/O pin <name> -- set to default MHz

No uPCore Transaction Model Input File specified for simulation. Defaulting to file <name>.

No valid register-to-register paths exist for clock <name>

No valid vector source file specified and default file <name> does not exist

No web browser has been set up for use with Quartus II software -- specify a web browser on the General Options tab in the Options dialog box (Tools menu)

Node <name>

Node <name>

Node <name>

Node <name>

Node <name>

Node <name>

Node <name>

Node <name>

Node <name>

Node <name>

Node <name>

Node <name>

Node <name>

Node <name> (dual-output)

Node <name> (not assigned to any LogicLock region)

Node <name> (not assigned to any LogicLock region)

Node <name> already assigned to pin <number> -- a node cannot be assigned to multiple pins

Node <name> already assigned to pin <number> -- a node cannot be assigned to multiple pins

Node <name> and node <name> belong to same parallel expander chain, but have conflicting embedded cell assignments

Node <name> and node <name> belong to the same carry or cascade chain but have conflicting location assignments

Node <name> assigned to <name> in Compiler Setting File is a dedicated input pin, but you cannot assign an output/bidir pin, input register, or macrocell to a dedicated input pin

Node <name> assigned to both location <name> and LogicLock region <name>

Node <name> assigned to custom region with corners <name> and <name>

Node <name> assigned to location <name>

Node <name> assigned to location <name>

Node <name> assigned to location <name>

Node <name> assigned to LogicLock region <name>

Node <name> assigned to LogicLock region <name> but also to location <location> -- used location assignment and ignored LogicLock region assignment

Node <name> assigned to LogicLock region <name> but back-annotated to location <location> outside region boundaries

Node <name> assigned to LogicLock region <name>, but node is pin -- ignored LogicLock region assignment on node

Node <name> assigned to LogicLock region with lower-left corner <location> and upper-right corner <location>

Node <name> back-annotated to location <name> in LogicLock region <name>, but location is not a legal location on the current device

Node <name> back-annotated to location <name> in LogicLock region <name>, but location is not a legal node location

Node <name> back-annotated to location <name> in LogicLock region <name>, but region does not have an origin

Node <name> because of assignment to custom region with corners <name> and <name>

Node <name> because of assignment to location <name>

Node <name> because of assignment to LogicLock region <name>

Node <name> cannot be assigned to dedicated negative pin <name> of type <type>

Node <name> cannot be assigned to more than one location

Node <name> does not exist

Node <name> fed by <type> has been assigned to pin <name>, but the corresponding negative pin <name> for the differential I/O standard is not available because it has been assigned to a different node

Node <name> fed by <type> has location assignment to <name>, but the location cannot be the negative pin for a differential I/O standard

Node <name> fed by a <type> has location assignment to <name>, but this location does not support a differential I/O standard

Node <name> feeding LVDS receiver <name> is not a simple pin

Node <name> feeds <type> and is assigned to location <name>, but this location cannot be the negative pin for a differential I/O standard

Node <name> feeds <type> and is assigned to location <name>, but this location must support a differential I/O standard

Node <name> feeds <type> port of ClockLock PLL <name>, but must not feed other destinations

Node <name> feeds a <type> and is assigned to location <name>, but the corresponding negative pin <name> for the differential I/O standard is not available because it has been assigned to a different node

Node <name> feeds input port <input clock, clock enable, or fbin> of <ClockLock PLL> <name>, but node does not include an input pin

Node <name> feeds input port of type <input clock> of <LVDS transmitter PLL> <name>, but node does not include an output clock port from LVDS receiver PLL or an input pin

Node <name> feeds the <type> input port of ClockLock PLL <name>, but the node must be an input pin

Node <name> feeds the <type> port of <type> <name>, but the node is not an input

Node <name> feeds the <type> port of ClockLock PLL <name>, but must not feed other destinations

Node <name> has <number> fan-out(s)

Node <name> has a different bus width than node <name>. Can't copy waveform data to node <name>.

Node <name> has a different signal type than node <name>. Waveform data will not be copied to node <name>.

Node <name> has a different value type than node <name>. Can't copy waveform data to node <name>.

Node <name> has illegal location assignment <name>

Node <name> has logic level of <number>

Node <name> has multiple location assignments

Node <name> has multiple location assignments -- using location <name>, assigned to <name>, and ignoring all other location assignments

Node <name> has multiple location assignments. Location <name> assigned to output port <name> and all other locations assignments ignored.

Node <name> has non-registered write enable-- attempting to initialize a RAM with non-registered write enable

Node <name> in compared vector source file is a different type from node in original vector source file

Node <name> in settings and configuration file <name> is illegal -- deleting illegal node

Node <name> is assigned to illegal location

Node <name> is assigned to illegal location <name>

Node <name> is assigned to location or region, but does not exist in design

Node <name> is assigned to pin <name> with the <name> I/O standard. However, the corresponding <name> negative pin <name> is not available because you assigned it to a different node.

Node <name> is fed by the <type> port of <type> <name>, but the node is not an output

Node <name> is fed non-globally

Node <name> is in LogicLock Region <name>

Node <name> is in LogicLock Region <name>

Node <name> is missing source

Node <name> is used as global clock input but is also used as another global input

Node <name> is used as global output enable input but also used as another global input

Node <name> moved from LogicLock region <name>

Node <name> must be at least two pads away from LVDS pin <name> in location BIN <name>

Node <name> must be placed at sublocation 0 (Fitter tried to place it at location <name>)

Node <name> of <ClockLock PLL> <name> assigned to pin <name>, but must be assigned to <type> pin

Node <name> of ClockLock PLL <name>, which is assigned to pin <name>, must be assigned to a <type> pin

Node <name> of the <type> <name>, which you assigned to pin <name>, should be assigned to a <type> pin

Node <name> of type <name> assigned to location <name>

Node <name> of type <name> cannot be placed on a dedicated clock pin because it has a fast input register packed with it

Node <name> of type <name> cannot be placed on a dedicated fast pin because it has a fast input register or fast output register with registered feedback packed with it

Node <name> of type <name> cannot be placed on a dedicated fast pin because it has a fast output register with registered feedback packed with it

Node <name> of type <name> cannot be placed on a dedicated fast pin or dedicated clock because it has a fast input register packed with it

Node <name> of type <name> must be assigned to a location consistent with other nodes in DSP block slice

Node <name> of type <type>

Node <name> of type <type>

Node <name> of type <type> assigned to LogicLock region <name>

Node <name> of type <type> cannot be assigned to location <name> of type <type>

Node <name> of type <type> cannot be assigned to the dedicated ClockLock PLL pin <name> of type <type>

Node <name> of type <type> cannot be assigned to the dedicated ClockLock PLL pin <name> of type <type>

Node <name> of type <type> has no legal location

Node <name> of type <type> in a Custom Region <location> to <location>

Node <name> will power-up low

Node <name>, assigned the <name> I/O standard, has location assignment to <name>, but location is an <name> negative pin

Node <name>, assigned the <name> I/O standard, is assigned to location <name>, but location must support the <name> I/O standard

Node <name>, assigned to ClockLock PLL clock enable pin <name>, must feeds ClockLock PLLs

Node <name>, assigned to ClockLock PLL clock feedback in pin <name>, must feed ClockLock PLLs

Node <name>, assigned to ClockLock PLL clock output pin <name>, must be fed by a ClockLock PLL

Node <name>, assigned to dedicated clock pin <name>, cannot globally feeds destinations in both polarities in the periphery

Node <name>, assigned to dedicated clock pin <name>, feeds non-clock ports globally. This assignment may affect the global behavior of the dedicated clock.

Node <name>, which feeds <input clk> of ClockLock PLL <name>, is assigned to pin <name>. This node feeds multiple ClockLock PLLs in design, but pin <name> can feed only one ClockLock PLL.

Node <name>, which feeds port of type <clkin> of <LVDS receiver PLL> <name>, cannot fan out to other destinations

Node <name>, which feeds the <type> port of ClockLock PLL <name>, cannot both feed other logic and act as the input clock to the ClockLock PLL when the ClockLock PLL is using the <type> port to feed clock input ports in the design

Node <name>, which is assigned to the <type> port of <type> <name>, clocks other logic and the <type> port feeds clock ports in the core

Node <name>, which you assigned, feeds port of type <type> of <type> <name>. This node cannot both clock other logic and act as input clock to ClockLock PLL when ClockLock PLL is using clock output port of type <type> to feed clock ports in design.

Node back-annotation in LogicLock region <name> breaks carry chain or cascade chain

Node cannot be used as operand for arithmetic comparison in Boolean expression

Node cannot be used as operand for arithmetic operator in Boolean expression

Node for output or bidirectional pin <name> is assigned to an I/O bank with LVDS receiver or transmitter channels

Node for output or bidirectional pin <name> is assigned to an LVDS receiver or LVDS transmitter channel pin

Node instance <name> instantiates undefined entity <name>

Node instance <name> must instantiate Text Design File entity <name> with named parameters

Node is assigned to pin <name>, but must be at least two pads away from VREF pin

Node is assigned to pin <name>, but must be within 16 pads of corresponding VREF pin

Node is constrained to region <region>

Node is part of a carry or cascade chain of size <number> that spans multiple LABs and starts with node <name>

Node line contains <name> and <name>, but may be named only once

Node name <name> cannot be edited because node is a lower-level node of node <name>

Node name <name> used by assignment of type <type> with value <text> is illegal

Node name <name> with type <type> in vector source file is of wrong type. Node type is a group of members of type <type>

Node named <name> removed during synthesis

Node of type <type> cannot be assigned to a <type> custom region

Node of type <type> cannot be assigned to a <type> LogicLock region

Node or bus name <name> already exists

Node or entity <name> assigned to LogicLock region <name> but also has Prevent Assignment to LogicLock Regions logic option turned on

Node or entity <name> assigned to LogicLock region <name> but also to LogicLock region <name>

Node or entity <name> assigned to undefined LogicLock region <name>

Node with the LVDS I/O standard is assigned to pin <name>, but corresponding LVDS negative pin <name> is not available because it is assigned to a different node

Nodes are assigned to locations, but do not exist in design

Nodes assigned to LogicLock region <name> but back-annotated to location outside region boundaries -- ignored LogicLock region assignment on nodes

Nodes have different radixes. Do you want to change the radix(es) of the selected node(s) to <text>?

Nodes of DSP block slice are assigned to illegal multiplier indices for operation mode <name>

Nodes of DSP block slice must be assigned to a location that has DSP blocks

Nodes of type <type> cannot be assigned to custom regions

Nodes of type <type> cannot be assigned to LogicLock region

Nodes or entities <name> and <name> belong to same clique <name>, but they are assigned to conflicting locations

Nodes or entities assigned to custom region

Nodes or entities assigned to LogicLock region <name> require <number> <name> but region can only contain <number> <name>

Nodes or entities assigned to LogicLock region <name> require <number> cells, but region contains only <number> cells

Nodes or entities assigned to LogicLock region <name> require <number> ESBs, but region can only contain <number> ESBS

Nodes or entities assigned to LogicLock region <name> require <number> LABs, but LogicLock region can only contain <number> LABs due to size limitation of an ancestor region

Nodes or entities assigned to LogicLock region <name> require more <text> than are available

Nodes or entities assigned to LogicLock region <name> require more ESBs than are available

Nodes or entities assigned to region <name> require <number> resources of type <type>, but the region can contain only <number> resources of this type

Nodes or entities assigned to region <name> require <number> signal pairs of types (<type>, <type>) and (<type>, <type>), but the specified region can contain only <number> signal pair(s)

Nodes or entities assigned to region <name> require <number> signals of type <type>, but the region can contain only <number> signals

Nodes or entities assigned to region <name> require <number> signals of type <type>, but the region can contain only <number> signals of this type

Nodes or entities assigned to region <name> require <number> signals of type <type>, but the specified region can contain only <number> signals

Nodes or entities assigned to region <name> require <number> signals of type <type>, but the specified region can contain only <number> signals

Nodes or entities assigned to region <name> require <number> signals of types <type> and <type>, but the specified region can contain only <number> signals

Nodes or entities assigned to region <name> require <number> signals of types <type> and <type>, but the specified region can contain only <number> signals

Nodes or entities assigned to region <name> require <number> signals of types <type>, <type>, <type>, <type>, and <type>, but the specified region can contain only <number> signals

Nodes or entities assigned to region <name> require <number> signals of types <type>, <type>, <type>, <type>, and <type>, but the specified region can contain only <number> signals

Nodes or entities assigned to region <name> require <number> signals of types <type>, <type>, <type>, and <type>, but the specified region can contain only <number> signals

Nodes or entities assigned to region <name> require <number> signals of types <type>, <type>, and <type>, but the specified region can contain only <number> signals

Nodes or entities assigned to region <name> require <number> signals of types <type>, <type>, and <type>, but the specified region can contain only <number> signals

Non-differential I/O pin <name> in pin location <name> (Pad_<number>) is too close to differential I/O pin <name> in pin location <name> (Pad_<number>)

Not all bits are used

Not allowed to move <number> registers because of timing assignments

Not allowed to move <number> registers because of user assignments

Not allowed to move <number> registers because they are connected to SERDES

Not allowed to move <number> registers because they are directly fed by input pins

Not allowed to move <number> registers because they are fed by input pins

Not allowed to move <number> registers because they are fed by registers in a different clock domain

Not allowed to move <number> registers because they feed clock or asynchronous control signals of other registers

Not allowed to move <number> registers because they feed output pins

Not allowed to move <number> registers because they feed output pins directly

Not allowed to move <number> registers because they feed registers in a different clock domain

Not allowed to move registers -- <number> registers affected

Not enough I/O pins used -- assigned too many buried macrocells

Not enough I/O pins used -- assigned too many input pins

Not enough I/O pins used in LAB <name> -- assigned too many buried macrocells in <name>

nSTATUS pin failed to go or remain high

nSTATUS pin failed to remain high on device <number>

Number of fan-out must be between 1 and 999999999 -- specify number of fan-out between 1 and 999999999

Number of group bits (<number>) on left of Boolean equation must be evenly divisible by number of group bits (<number>) on right

Number of group bits (<number>) on left of Boolean equation must match or be evenly divisible by number of group bits (<number>) on right

Number of input ports in cell <name> of EDIF Input File cannot be greater than the number of input ports in Library Mapping File <name>

Number of memory words in MIF or HEX File must be greater than zero

Number of memory words in MIF or HEX File must not exceed <number>

Number of nodes must be between 1 and 999999999 -- specify number of nodes between 1 and 999999999

Number of output ports in cell <name> of EDIF Input File cannot be greater than the number of output ports in Library Mapping File <name>

Number of rows selected must equal the number of rows to be pasted

Number of words must not exceed <number>

Number representation error: illegal value <text> for <name> parameter

Numbers cannot be assigned to nodes

Numerical value <text> that is assigned to state has fewer bits than the state. Functional simulation may not match timing simulation

Numerical value <text> that is assigned to state has more bits than the state -- attempted to fit value into state

Numerical value <text> that is assigned to state has more bits than the state -- truncating value to fit in state

O

Offloading acquired data

On-chip termination used on banks 3, 4, 7, or 8 is not supported for EP1S40 engineering sample devices. Recompile for EP1S40 production ordering code devices. For more information, contact Altera Applications.

One coordinate of custom region <name> contains illegal syntax

One group in operation has <number> bits and a second group has <number> bits, but the groups must be the same size

One group in operation has <number> bits and a second group has <number> bits, but the groups must be the same size

One or more clock domains do not have fmax value. Do you want to open HardCopy HC20K Power Calculator page on Altera web site?

One or more clock settings are derived from the absolute clock settings <name>. Deleting the absolute clock settings also deletes all derived clock settings.

One or more clock settings are derived from the absolute clock settings <name>. Deleting the absolute clock settings also deletes all derived clock settings.

One or more Compiler settings must exist in the project before creating Simulator settings

One or more Compiler settings must exist in the project before you can open the Assignment Organizer

One or more extclk ports of enhanced PLL <name> must feed output pins when OPERATION_MODE parameter is set to EXTERNAL_FEEDBACK or ZERO_DELAY_BUFFER

One or more files in directory <name> have the same name as files located in one or more library directories. Do you want to rename the files in directory <name> (the prefix "old" will be added to the files)?

One or more illegal characters are contained in <name>

One or more illegal characters are contained in <name>

One or more LogicLock regions in your design contains errors and cannot be displayed in the Floorplan Editor -- use the LogicLock Regions window to correct errors

One or more nodes in carry chain have location assignments

One or more pins use input reference <name>, but that input reference is not enabled

One or more Simulator settings must exist in the project before you can open the Assignment Organizer

Open a project before creating new Compiler, Simulator or software build settings

OpenCore Plus time-limited core <name> may be used for hardware evaluation only

Opening HardCopy HC20K Power Calculator page on Altera web site. Click Help for more information. Sending the following information to HardCopy HC20K Power Calculator page: * target device * target device package * temperature grade of target device * clock domain fmax * number of flipflops * number of logic elements * number of output and bidirectional pins * number of Embedded System Blocks. Manually enter all other relevant information in the HardCopy HC20K Power Calculator page, including the following information: * average logic element toggle (defaults to 12.5%) * average capacitive load (defaults to 10pF) * DC output power * ambient temperature. After entering information in HardCopy HC20K Power Calculator page, click Calculate.

Operating frequency for HSDI PLL <name> is <text>, but must be within range of <text> to <text>

Operation canceled

OPERATION_MODE parameter for PLL <name> has unsupported value <text>

OPERATION_MODE parameter of ClockLock PLL <name> must be set to LVDS when clock2 output port drives logic

OPERATION_MODE parameter value for WYSIWYG primitive <name> is illegal

OPERATION_MODE parameter value for WYSIWYG primitive <name> must be specified

Options Statement contains more than one <name> option -- used only first instance of option

Options Statement contains more than one BIT0 option -- using only first BIT0 option

Orientation of device in socket is backwards

Out of memory

Out of memory

Output <name> of LVDS receiver <name> has too many fanouts

Output <name> of LVDS receiver <name> is connected to non-registered port

Output <name> of LVDS receiver <name> must connect to a register. In x4 mode, the receiver should be follwed by two registers both clocked by the PLL of the LVDS receiver x1 mode -- the closest register to the receiver should have a inverted clock in x1 mode.

Output <name> of LVDS receiver <name> should connect to a register

Output <name> of LVDS transmitter <name> is not a simple output pin because <text>

Output <name> of LVDS transmitter <name> must feed an output pin directly

Output clock clk<port number> of enhanced PLL <name> drives both regional and global clocks

Output clock frequency <number> of GXB receiver channel atom <name> is illegal -- output clock frequency value must be in the frequency range of <number> to <number>

Output clocks of enhanced PLL <name> need <number> regional clocks but the PLL cannot use more than <number> regional clocks

Output Enable Register Duplication turned on for the following node -- ignored LogicLock region or custom region assignment on node

Output enable registers in I/O cell <name> will power up low

Output Enable signal can't be driven by <name> which is assigned to location <name>

Output frequency of <number> specified for ClockLock PLL <name> is greater than maximum operational frequency of <number> for LVDS receiver or transmitter to core interface

Output frequency of <number> specified for ClockLock PLL <name> is greater than maximum operational frequency permitted for <number> destination(s)

Output I/O cell <name> has differential I/O standards, but is assigned to a pin that cannot be used as differential output

Output of PLL <name> cannot be connected to its own clock input

Output or bidirectional I/O cell <name> has HSTL Class II I/O standard and is assigned to pin <name>, but pin <name> does not support this output I/O standard

Output or bidirectional pin <name> in pin location <name> (Pad_<number>) is too close to VREF pin in pin location <name> (Pad_<number>)

Output pin <name> cannot have a differential I/O standard other than the LVDS I/O standard

Output pin <name> defined with group range in Subdesign Section cannot be defined with different group range in Variable Section

Output pin <name> of port <type> can be fed by only ClockLock PLL <name> because ClockLock PLL output pin <name> is user-assigned to <name>

Output pin <name>, external output clock of PLL <name>, uses I/O standard <name> and has output clock frequency of <name>, but target device can support only maximum output clock frequency of <name> for I/O standard

Output pins are stuck at VCC or GND

Output port <clk0 or clk1> of <ClockLock PLL> <name> feeds node <name>, but output port must feed an output pin

Output port <name> assigned to location <name>

Output port <name> of <type> PLL <name> cannot drive a SERDES receiver or transmitter

Output port <name> of enhanced PLL <name> must be connected

Output port <name> of enhanced PLL <name> must feed an output pin

Output port <name> of enhanced PLL <name> must feed an output pin

Output port <name> of GXB receiver channel atom <name> cannot be connected because <text>

Output port <name> of GXB receiver channel atom <name> in channel 0 must be connected because <text>

Output port <name> of GXB receiver channel atom <name> in channel 0 must connect to input port <name> of a GXB receiver channel atom

Output port <name> of GXB receiver channel atom <name> must be connected because <text>

Output port <name> of GXB receiver channel atom <name> must be connected to input port <name>[<number>] of XGMII state machine atom

Output port <name> of GXB receiver channel atom <name> must be connected to input port <name>[<number>] of XGMII state machine atom because <text>

Output port <name> of GXB transmitter channel atom <name> must connect to input port <name> of XGMII state machine atom

Output port <name> of LVDS transmitter <name> must have only one fan-out

Output port <name> of PLL <name> cannot drive a SERDES receiver or transmitter when the PLL_TYPE parameter is set to FAST

Output port <name> of PLL <name> feeds an output pin via global clocks -- there is no preliminary jitter specification, as it is pending silicon characterization. Use the PLL dedicated clock outputs for better jitter performance

Output port <name> of the <name> <name> is missing source

Output port <name> of XGMII state machine atom <name> must connect to input port <name> of atom <name>

Output port <name>.<name> cannot be assigned a value

Output port <name>[<number>] of GXB receiver channel atom <name> cannot be connected because <text>

Output port <name>[<number>] of GXB receiver channel atom <name> must be connected because <text>

Output port <name>[<number>] of GXB receiver channel atom <name> must be connected only to input port <name>[<number>] of an XGMII state machine atom

Output port <name>[<number>] of GXB receiver channel atom <name> must feed only output port <name>[<number>] of a GXB transmitter channel atom in the same channel because <name>

output port <name>[<number>] of GXB transmitter channel atom <name> must connect to input port <name>[<number>] of a GXB receiver channel atom

output port <name>[<number>] of GXB transmitter channel atom <name> must connect to input port <name>[<number>] of XGMII state machine atom

Output port <name>[<number>] of XGMII state machine atom <name> must connect to input port <name> of atom <name> in channel <number>

Output port <name>[<number>] of XGMII state machine atom <name> must connect to input port <name>[<number>] of atom <name> in channel <number>

Output port of type <clk0 or clk1> of <ClockLock PLL> <name> must feed only clock input ports

Output port of type <clk0 or clk1> of <ClockLock PLL> <name> must feed only clock input ports and no more than one output pin

Output port of type <type> of ClockLock PLL <name> must feed clock input ports

Output port(s) cannot have default value of GND or VCC

Output ports of HSDI transmitter <name> must be connected directly to output pins

Output registers in I/O cell <name> will power up low

Output(s) of LVDS transmitter <name> must be connected directly to output I/O node(s)

Overwriting existing resynthesis output files. Do you want to continue?

P

padio output port of DQS I/O pin <name> must be connected to a bidirectional I/O pin in the device

Page percentage when printing floorplans must be between <number> and <number>

Page settings for Programmer Object File for Local Update are illegal

PALACE software error: <text>

PALACE software information: <text>

PALACE software warning: <text>

Parallel expander chain length <number> exceeds limit of current device. Change length to <number>

Parallel expander chain of WYSIWYG MCELL primitive <name> contains too many (at least <number>) literal inputs feeding into the macrocell

Parallel Expanders conflict -- node/pin <name> assigned to <name> cannot borrow parallel expanders

Parallel Expanders conflict -- node/pin <name> assigned to <name> conflicts with node/pin <name> assigned to <name>

Parameter <name> cannot be assigned more than one value

Parameter <name> is not supported for WYSIWYG primitive <name>

Parameter assignment name: <name>

Parameter error: DEDICATED_MULTIPLIER_CIRCUITRY parameter with value <text> must be set to AUTO, YES, or NO

Parameter error: illegal value <text> for DEDICATED_MULTIPLIER_CIRCUITRY parameter

Parameter error: illegal value for DCFIFO_INVALID_CLOCKS_ARE_SYNCHRONIZED parameter of a FIFO buffer

Parameter error: illegal value for LPM_SHOWAHEAD parameter of a FIFO buffer

Parameter error: illegal value for OVERFLOW_CHECKING parameter of a FIFO buffer

Parameter error: illegal value for UNDERFLOW_CHECKING parameter of a FIFO buffer

Parameter error: illegal value for USE_EAB parameter of a FIFO buffer

Parameter error: LPM_DECODES parameter value is <integer>, but must be greater than 0

Parameter error: LPM_DECODES parameter value is <integer>, but must be less than or equal to 2 to the power of the value <integer> of LPM_WIDTH parameter

Parameter error: LPM_REPRESENTATION parameter with value <text> must be set to SIGNED or UNSIGNED

Parameter error: LPM_SIZE parameter value is <integer>, but must be greater than 1

Parameter error: LPM_SIZE parameter value is <integer>, but must be less than or equal to 2 to the power of the value <integer> of LPM_WIDTHS parameter

Parameter error: LPM_WIDTH parameter value is <integer>, but must be greater than 0

Parameter error: LPM_WIDTH parameter value is <integer>, but must be greater than 0

Parameter error: LPM_WIDTHS parameter value is <integer>, but must be greater than 0

Parameter error: parameter <text> with value <text> must be set to YES or NO

Parameter error: RIGHT_SHIFT_DISTANCE parameter value is <integer>, but must be less than value <integer> of WIDTH_OUT parameter

Parameter error: USE_EAB parameter with value <text> must be set to ON or OFF

Parameter error: value <integer> for NUMBER_OF_COEFFICIENTS parameter is greater than value <integer> of WIDTH_S parameter

Parameter error: value <integer> for SHIFT_DISTANCE parameter of lpm_shiftreg megafunction must be less than or equal to value <integer> for LPM_WIDTH parameter

Parameter error: value <integer> of TOTAL_LATENCY parameter is less than the minimum legal value <integer>

Parameter error: value for LPM_NUMWORDS parameter of a FIFO buffer must be greater than or equal to 2

Parameter error: value for LPM_WIDTH parameter of a FIFO buffer must be greater than or equal to 1

Parameter error: value of <name> parameter must be greater than 0

Parameter error: value of <name> parameter of a FIFO buffer must be greater than or equal to <integer>

Parameter error: value of <name> parameter of a FIFO buffer must be less than or equal to value of <integer> of LPM_NUMWORDS parameter

Parameter error: value of <name> parameter of a FIFO buffer must be ON or OFF

Parameter error: WIDTH_IN parameter value is <integer>, but must be greater than 0

Parameter error: WIDTH_IN parameter value is <integer>, but must be less than or equal to value <integer> of WIDTH_OUT parameter

Parameter error: WIDTH_OUT parameter value is <integer>, but must be greater than 0

Parameter or block setting <text> at line <number> in file <name> contains semantic error

Parameters cannot be specified for primitives

Passive programming files do not contain initialization data

Passive Serial mode supports only SRAM Object Files

Passwords do not match

Pattern Section of vector source file <name> contains incomplete pattern

PCI I/O logic option turned off for pin <name> -- Quartus II software automatically turns it on for LVDS or LVPECL I/O standard

PCI I/O logic option turned on for <name> pin

Perform a smart compilation before routing SignalProbe signals

Performed smart compilation to reroute SignalTap II post-fitting nodes

Performing gate-level register retiming

Performing hierarchical synthesis which affects fitting and performance

Performing verification of type <type> on device <number>

Performing verification of type <type> on device(s)

Peripheral <name> at register base address <text>

pexpin port of ATOM <name> cannot be VCC, GND, inverted, direct from pin, or from non-parallel expander output port on another ATOM

pexpin port of WYSIWYG primitive <name> cannot be VCC, GND, inverted, direct from pin, or from non-parallel expander output port on another WYSIWYG primitive

pexpout port of ATOM <name> must positively feed pexpin port

Pexpout port of WYSIWYG primitive <name> must positively feed pexpin port, and have only one fanout

pfd frequency value <number> Mhz is less than ten times the bandwidth value <number> Mhz -- pfd frequency value must be at least ten times the bandwidth value

pgmout port <number> of ATOM <name> drives cell <name>, which <name>, but pgmout port must drive an output pin

pgmout port <number> of atom <name> has <number> fan-outs -- pgmout port must have only one fan-out

Pin <name>

Pin <name> assigned to <name> in Compiler Setting File is a VREFA pin, but the pin already drives a VREFA pin

Pin <name> assigned to <name> in Compiler Setting File is a VREFB pin, but the pin already drives a VREFB pin

Pin <name> cannot connect to more than one source signal

Pin <name> defined in Subdesign Section as input, machine input, or machine output pin cannot be defined in Register Declaration

Pin <name> does not support I/O standard <name> for <name>

Pin <name> does not support I/O standard <name> with Current Strength <name> for location <name>

Pin <name> does not support Termination logic option setting <name> for I/O pin <name> in design

Pin <name> drives fast regional clock, but cannot be placed in fast clock pin position

Pin <name> drives global clock, but is not placed in a dedicated clock pin position

Pin <name> drives regional clock, but is not placed in dedicated clock pin position

Pin <name> driving clock input pin of fast PLL <name> does not have same I/O standard as other differential I/O pins driven by that PLL -- Fitter will automatically assign <name> I/O standard to pin

Pin <name> has no register for Power-Up High option

Pin <name> in I/O bank <number> is using I/O standard <name>, but has a VCCIO requirement that is incompatible with other input and/or bidirectional pins in that bank that use VCCIO <number>

Pin <name> in I/O bank <number> is using I/O standard <name>, but has a VCCIO requirement that is incompatible with other output or bidirectional pins in that bank that use VCCIO <number>

Pin <name> in I/O bank <number> is using I/O standard <name>, but has a VREF requirement that is incompatible with other input or bidirectional pins in that bank that use VREF <number>

Pin <name> is assigned to a dedicated clock pin, but none of its destinations can use global signals

Pin <name> is assigned to JTAG pin <name> in Compiler Setting File, but the pin already drives a JTAG pin

Pin <name> is assigned to location <name>, but must be at least two pads away from VREF pin <name>

Pin <name> is assigned to pin location <name> (<name>)

Pin <name> is illegal

Pin <name> is too close to LVDS pin <name> in location BIN <name>

Pin <name> is too close to LVDS pin <name> in location BIN <name> after device migration

Pin <name> is virtual input pin

Pin <name> is virtual output pin

Pin <name> not connected

Pin <name> of LVDS receiver <name> must have only one fan-out

Pin <name> other than the HSDI clock pin (HSDI_CLK1 or HSDI_CLK2) is feeding HSDI PLL in Clock Data Recovery mode

Pin <name> other than the HSDI clock pin (HSDI_CLK1 or HSDI_CLK2) is feeding HSDI PLL in Clock Data Recovery mode

Pin <name> overlaps another pin, block, or symbol

Pin <name> overlaps another pin, block, or symbol

Pin <name> stuck at <value>

Pin <name> uses I/O standard <name> but has no input reference assignment

Pin <name> uses I/O standard <name>, but shares an input reference with pins using I/O standard <name>

Pin <name> uses I/O standard <name>, which is incompatible with the VCCIO setting for both I/O banks (I/O Bank 1: <name>, I/O Bank 2: <name>)

Pin <name> uses I/O standard <name>, which is incompatible with the VCCIO setting for the I/O bank containing the pin (I/O bank <number>: <name>)

Pin <name> with <name> I/O standard must be driven by external clock output pin of PLL

Pin <name>, which feeds or is fed by port of type <type>, and pin <name>, which feeds or is fed by port of type <type>, of ClockLock PLL <name> do not have matching I/O standards

Pin <name>, which feeds or is fed by the <type> port and pin <name>, which feeds or is fed by the <type> port, of ClockLock PLL <name> must have the same I/O standards

Pin <name>, which feeds or is fed by the <type> port of ClockLock PLL <name>, is assigned an illegal I/O standard

Pin assignment <name> in Compiler Settings File is a power pin, but you cannot assign a pin to a power pin

Pin continuity failure on pin <name>

Pin name <name> is illegal

Pin name <name>, assigned to an I/O cell at location <number>, <number> sublocation <number>, is not connected to the I/O cell on the device

Pin name <name>, assigned to an I/O cell at location <number>, <number> sublocation <number>, is not connected to the I/O cell on the device selected for migration

Pin other than global clock pin (clk1, clk2, or clk4) is feeding HSDI PLL in LVDS mode

Pins in I/O bank are assigned I/O standards with different output voltages

Pins in I/O bank are assigned two different I/O standards

Pins in I/O bank are assigned two different I/O standards

Placed <number> cliques

Placed <type> clique <name> with <number> macrocells

Placed node <name> inside boundaries of LogicLock region <name>

Placement of stand-alone GXB transmitter PLLs is not supported in current version of Quartus II software

Placement requirements for differential I/O standards may not be made for some nodes

Placing the following cells in this region

Please type a Tcl Script File name

PLL <name> cannot be in <mode> because SCAN_CHAIN parameter is set to SHORT

PLL <name> cannot have value for <name> parameter

PLL <name> feeds <number> channels of HSDI <transmitter or receiver>, but the maximum number of HSDI channels that a PLL can feed in the current device is <number>

PLL <name> has <CLKn_COUNTER or EXTCLKn_COUNTER> parameter with value <text>, but that value is already specified by another <CLKn_COUNTER or EXTCLKn_COUNTER> parameter

PLL <name> has <number> time delay for <name> parameter, but time delay must be between <number> ps and <number> ps, with a resolution of 250 ps

PLL <name> has illegal duty cycle value <number> -- duty cycle must be more than 40% or less than 60% to ensure that the lock filter functions correctly

PLL <name> has illegal duty cycle value <number> for <name> parameter -- duty cycle must be more than 40% or less than 60% to ensure that the lock filter functions correctly

PLL <name> has illegal or non-numeric value <number> for <name> parameter

PLL <name> has illegal or non-numeric value <text> for <name> parameter

PLL <name> has illegal unit <text> for <name> parameter -- legal unit should be <text>

PLL <name> has illegal value <number> for parameter <name>

PLL <name> in <name> device requires a duty cycle between 40 percent and 60 percent, but input clock signal <name> has a duty cycle of <number>

PLL <name> is <text> and DQS I/O pin <name> is <text>

PLL <name> is merged into PLL <name>

PLL <name> must contain <name> <signal or parameter>

PLL <name> must contain internal parameter <name>

PLL <name> must have BANDWIDTH_TYPE parameter set to LOW or HIGH when PLL_TYPE parameter is set to CDR

PLL <name> must have OPERATION_MODE parameter set to NORMAL when PLL_TYPE parameter is set to CDR

PLL <name> must use <fbin port or FEEDBACK_SOURCE parameter> because it is in EXTERNAL_FEEDBACK mode

PLL <name> must use <inclk0 or inclk1> port because it is specified in PRIMARY_CLOCK parameter

PLL <name> of <name> is <text> and DQS I/O pin <name> is <text>

PLL <name> of type <type> cannot be in <mode>

PLL <name> uses clock settings parameter <name> -- clock settings are no longer supported for PLLs

PLL <name>, which feeds DQS I/O pins, must be driven by a system clock

PLL Compensation logic option is specified for several output pins that are fed by <name> port of enhanced PLL <name>

PLL enable pin does not support differential I/O standards

PLL parameter value <name> is not in range allowed for parameter

PLL_TYPE parameter for PLL <name> has unsupported value <text>

Port <name> already has a source. Ignoring net <name>.

Port <name> does not exist in macrofunction <name>

Port <name> does not exist in macrofunction <name>. The range of the port is wider in the macrofunction than in the design.

Port <name> does not exist in primitive <name> of instance <name>

Port <name> for cell <name> does not exist in Library Mapping File <name>

Port <name> in macrofunction <name> has no range declared -- Quartus II software will connect the port to pin <name> because the pin is a member of a single bit bus with the same name as the port

Port <name> in Module Instantiation cannot contain logical negation operator (!)

Port <name> of <type> PLL <name> cannot be implemented

Port <name> of ClockLock PLL <name> cannot feed I/O cells both positively and negatively

Port <name> of enhanced PLL <name> can only feed output pins

Port <name> of enhanced PLL <name> cannot feed more than <number> output pins

Port <name> of enhanced PLL <name> cannot feed more than <number> single-ended or <number> differential output pins

Port <name> of type <name> and instance <name> is missing source signal

Port <name> of type <name> of instance <name> is missing source signal

Port <name> of XGMII state machine atom <name> has width of <number>, but must have width of <number>

Port <name> width exceeds memory block type <type> limit of <number> bits

Port <type> output frequency of <number> for PLL <name> must be in the frequency range of <number> to <number>

Port A write enable register of Embedded System Block memory segment <name> was asynchronously reset at time <time> during a write cycle

Port at position <number> does not exist in macrofunction <name>

Port B write enable register of Embedded System Block memory segment <name> was asynchronously reset at time <time> during a write cycle

Port count (<number>) for instance of logic function <name> must agree with Function Prototype port count (<number>)

Port direction mismatch for entity <name> at port <name>. Upper entity is expecting <name> pin while lower entity is using <name> pin.

Port of type <clk0 or clk1> of <LVDS transmitter PLL> <name> must feed <LVDS transmitter>

Port of type <clk0 or clk1> of ClockLock PLL <name> cannot feed destinations that are inverted

Port of type <clk0 or clk1> of LVDS receiver PLL <name> must feed LVDS receiver

Port of type <clkout> must be connected when ClockLock PLL <name> is in zero delay buffer mode

Port of type <clock0> of <LVDS Receiver PLL> <name> must feed only clk0 port of LVDS receiver

Port of type <clock0> of <LVDS transmitter PLL> <name> must feed only clk0 port of LVDS transmitter

Port of type <clock1> of <LVDS transmitter PLL> <name> must fan out only to clk1 port of LVDS transmitter cell and to only one output pin

Port of type <fbin> must be connected when ClockLock PLL <name> is in external feedback mode

Port of type <type> in ClockLock PLL <name> must have source

Port of type <type> must be connected for ClockLock PLL <name> that is in zero delay buffer mode

Port of type <type> of <type> <name> cannot feed to more than <number> destination(s)

Port of type <type> of <type> <name> contains fan-out to illegal destinations

Port of type <type> of <type> <name> is inverted

Port of type <type> of <type> <name> must have source

Port of type <type> of ClockLock PLL <name> cannot feed more than <number> destination(s)

Port of type <type> of LVDS transmitter PLL <name> can fan out only to clk1 port of LVDS transmitter cell and/or core logic through global clock lines

Port of type <type> of node <name> is being fed non-globally

Port of type <type> of node <name> is fed non-globally

Port of type <type> of node <name> is fed non-globally

Port of type <type> of the <type> <name> fans out to non-global destinations, but port of type <type> can feed only global destinations

Port of type <type> of the <type> <name> has fan-out to non-global destinations, but the <type> port can only feed globally

Port of type <type> of the <type> <name> has fanout to non-global destinations, but port of type <type> can feed only globally

Port of type ClockLock clock0 of <type> <name> is used as an output and the dedicated clock pin CLK1 is assigned

Port range <range> must match in Net Declaration and Module Declaration

Port type <type> of node <name> is fed globally, but port is not a clock port

Power estimation end time <time> exceeds simulation end time -- Used simulation end time <time>

Power estimation values of device <name> are preliminary

Power-Up High option on register <name> will override Power-Up High option on pin <name>

Power-up level of register <name> is not specified -- using unspecified power-up level

Preserve Hierarchical Boundary option on entity <name> not set to Firm

Preserve Hierarchical Boundary option on entity <name> set to Relaxed

Preset and clear are both active at time <time> on register <name>

Presettable registers will power up high

PrimeTime software error: <text>

PrimeTime software information: <text>

PrimeTime software warning: <text>

Primitive <name> of instance <name> not used

Primitive <name> of type <type> cannot feed CASCADE primitive <name> because the primitive already contains fan-out to one or more CASCADE primitives

Process is currently running. Processing design using previous settings -- changes made to settings since the process started will not take effect until you restart the process.

Process is currently running. Processing design using previous Simulator settings -- changes made to Simulator settings will not take effect until you reinitialize the Simulator.

Processed Auto SLD Node Entity section keyword <name>

Processed DEDICATED_MULTIPLIER_CIRCUITRY parameter with setting <name> for node <name>

Processed DSP block balancing assignment <name> for node <name>

Processed Memory Initialization File <name> during smart compilation

Processing of Quartus II <number> started at time <number>

Processor type <name> specified in the System Build Descriptor File <name> does not match type of selected device <name>

Product term logic cell <name> must have no more than 32 inputs

Program the device to continue

Programmer Object File cannot contain Hexadecimal (Intel Format) File in Main Block Data item and SRAM Object File with either remote update enabled or local update enabled in SOF Data item

Programmer Object File does not have <name> update turned on

Programmer Object File is corrupted

Programming device

Programming device <number>

Programming device(s)

Programming error: <text>

Programming failed

Programming file <name> selected for replacement contains device <name>, which is incompatible with current device <name> in device chain. Proceeding will cause new device associated with selected programming file to replace current device. Do you want to replace programming file?

Programming file cannot be added for association with selected device in device chain if programming option, Examine, is turned on for that device

Programming file of type <type> is not supported

Programming files may not configure PLD portion of Excalibur <name> device because <number> stripe signal(s) were not routed correctly -- refer to <name> errata sheet

Programming hardware setup is illegal

Programming status: <text>

Programming succeeded

Project <name> already exists

Project <name> already exists in directory <name>. Do you want to open this project?

Project <name> does not exist

project add_assignment <entity> <section_identifier> <source> <destination> <variable> <value>

project add_parameter <entity> <destination> <variable> <value>

Project contains multiple Chip sections in the Compiler Settings File and requires more than one device, but the Quartus II software does not support multidevice partitioning

Project directory <name> already contains a project. If the projects share the same files, edits made while working on one project could affect the other project. Do you want to select a different project directory?

Project does not contain a Compiler Settings File -- use Compiler Settings wizard to specify compilation focus point

Project does not contain a Simulator Settings File -- use Simulator Settings wizard to specify simulation focus point

Project does not contain a Software Build Settings File -- use the Quartus II software to create software build settings

Project name contains an illegal character

project remove_assignment <entity> <section_identifier> <source> <destination> <variable> <value>

project remove_parameter <entity> <destination> <variable> <value>

Project requires <number> ClockLock PLLs, but the selected device can contain only <number> ClockLock PLLs

Project requires <number> ClockLock PLLs, but the selected device can contain only <number> ClockLock PLLs

Project requires <number> dedicated global signal pins, but the selected device can contain only <number> dedicated global signal pins

Project requires <number> dedicated global signal pins, but the selected device can contain only <number> dedicated global signal pins

Project requires <number> dedicated global signal pins, but the selected device can contain only <number> dedicated global signal pins

Project requires <number> differential I/O-compatible pins, but the target device can contain only <number> differential I/O-compatible pins

Project requires <number> Embedded Array Blocks for RAM, but the selected device can contain only <number> EABs

Project requires <number> Embedded System Blocks for content-addressable memory, but the selected device can contain only <number> ESBs

Project requires <number> Embedded System Blocks for content-addressable memory, but the selected device can contain only <number> ESBs

Project requires <number> Embedded System Blocks for product-term logic, but the selected device can contain only <number> ESBs

Project requires <number> Embedded System Blocks for RAM and product-term logic, but the selected device can contain only <number> ESBs

Project requires <number> Embedded System Blocks for RAM, but the selected device can contain only <number> ESBs

Project requires <number> Embedded System Blocks for RAM, but the selected device can contain only <number> ESBs

Project requires <number> Embedded System Blocks for RAM, but the selected device can contain only <number> ESBs

Project requires <number> Embedded System Blocks for RAM, but the selected device can contain only <number> ESBs

Project requires <number> enhanced PLLs that have the SCAN_CHAIN parameter set to SHORT, but the target device can contain only <number> enhanced PLLs of this type

Project requires <number> enhanced PLLs that use the fbin port or use more than one extclk port, but the target device has only <number> enhanced PLLs of this type available

Project requires <number> enhanced PLLs, but the target device has only <number> enhanced PLLs

Project requires <number> ESBs, but the selected device can contain only <number> ESBs

Project requires <number> fast or enhanced PLLs, but the target device can contain only <number> fast or enhanced PLLs

Project requires <number> fast PLLs that support high-speed differential I/O nodes, but target device can contain only <number> fast PLLs

Project requires <number> fast PLLs, but the target device can contain only <number> fast PLLs

Project requires <number> fast PLLs, but the target device has only <number> fast PLLs

Project requires <number> fast, enhanced, or GXB transmitter or receiver PLLs, but target device can contain only <number> PLLs

Project requires <number> general purpose I/O cells, but the selected device can contain only <number> general purpose I/O pins

Project requires <number> general-purpose I/O pins, but target device can contain only <number> general-purpose I/O pins

Project requires <number> global signals, but the selected device can contain only <number> global signals

Project requires <number> global signals, but the selected device can contain only <number> global signals

Project requires <number> global signals, but the selected device can contain only <number> global signals

Project requires <number> GXB receiver channels, but the target device can contain only <number> GXB receiver channels

Project requires <number> GXB transmitter channels, but the target device can contain only <number> GXB transmitter channels

Project requires <number> GXB transmitter PLLs, but the target device can contain only <number> GXB transmitter PLLs

Project requires <number> HSDI <transmitter(s) or receiver(s)> and <number> Flexible-LVDS <transmitter(s) or receiver(s)>, but selected device can contain only <number> HSDI <transmitter(s) or receiver(s)> and <number> Flexible-LVDS <transmitter(s) or receiver(s)>

Project requires <number> HSDI <transmitter(s) or receiver(s)>, but selected device can contain only <number> HSDI <transmitter(s) or receiver(s)>

Project requires <number> HSDI PLLs to drive <name>-mode HSDI receivers, but the selected device can only support <number> HSDI PLL driving <name>-mode HSDI receivers.

Project requires <number> HSDI PLLs to drive <name>-mode HSDI transmitters, but the selected device can only support <number> HSDI PLL driving <name>-mode HSDI transmitters.

Project requires <number> HSDI PLLs, but selected device can contain only <number> HSDI PLLs

Project requires <number> HSDI receivers with clockout signals, but selected device can have only <number> HSDI receivers with these clockout signals

Project requires <number> HSDI receivers, but selected device can contain only <number> HSDI receivers

Project requires <number> HSDI transmitters with clockout signals, but selected device can have only <number> HSDI transmitters with these clockout signals

Project requires <number> HSDI transmitters, but selected device can contain only <number> HSDI transmitters

Project requires <number> I/O cell signals of type <type> and <type>, but the selected device can contain only <number> I/O cell signals

Project requires <number> I/O cell signals of type <type> and <type>, but the selected device can contain only <number> I/O cell signals

Project requires <number> I/O cell signals of type <type>, <type> and <type>, but the selected device can contain only <number> I/O cell signals

Project requires <number> I/O cell signals of type <type>, <type> and <type>, but the selected device can contain only <number> I/O cell signals

Project requires <number> I/O cell signals of type <type>, <type>, <type> and <type>, but the selected device can contain only <number> I/O cell signals

Project requires <number> I/O cell signals of type <type>, <type>, <type> and <type>, but the selected device can contain only <number> I/O cell signals

Project requires <number> I/O cell signals of type <type>, but the selected device can contain only <number> I/O cell signals

Project requires <number> I/O cell signals of type <type>, but the selected device can contain only <number> I/O cell signals

Project requires <number> I/O pins, but the selected device can contain only <number> I/O pins

Project requires <number> I/O pins, but the selected device can contain only <number> I/O pins

Project requires <number> I/O pins, but the selected device can contain only <number> I/O pins

Project requires <number> I/O pins, but the selected device can contain only <number> I/O pins

Project requires <number> input pins, but the selected device can contain only <number> input pins

Project requires <number> input pins, but the selected device can contain only <number> input pins

Project requires <number> input pins, but the selected device can contain only <number> input pins

Project requires <number> LABs from <number> logic cells, but the selected device can contain only <number> LABs

Project requires <number> logic cells be placed in LE1 of a LAB, but the selected device can contain only <number> logic cells in LE1

Project requires <number> logic cells be placed in LE2 of a LAB, but the selected device can contain only <number> logic cells in LE2

Project requires <number> logic cells, but the selected device can contain only <number> logic cells

Project requires <number> logic cells, but the selected device can contain only <number> logic cells

Project requires <number> logic cells, but the selected device can contain only <number> logic cells

Project requires <number> logic-driven global signals, but the selected device can contain only <number> logic-driven global signals

Project requires <number> logic-driven global signals, but the selected device can contain only <number> logic-driven global signals

Project requires <number> logic-driven global signals, but the selected device can contain only <number> logic-driven global signals

Project requires <number> LVDS I/O pins operating in LVDS bypass (x1) mode, but the selected device does not support this feature

Project requires <number> LVDS receiver PLLs, but the selected device can contain only <number> LVDS receiver PLLs

Project requires <number> LVDS Receiver PLLs, but the selected device can contain only <number> LVDS Receiver PLLs

Project requires <number> LVDS receivers, but the selected device can contain only <number> LVDS receivers

Project requires <number> LVDS transmitter PLLs, but the selected device can contain only <number> LVDS transmitter PLLs

Project requires <number> LVDS Transmitter PLLs, but the selected device can contain only <number> LVDS Transmitter PLLs

Project requires <number> LVDS transmitters, but the selected device can contain only <number> LVDS transmitters

Project requires <number> output pins, but the selected device can contain only <number> output pins

Project requires <number> output pins, but the selected device can contain only <number> output pins

Project requires <number> output pins, but the selected device can contain only <number> output pins

Project requires <number> output pins, including <number> reserved dual-purpose configuration pins, but the selected device can contain only <number> output pins

Project requires <number> output pins, including <number> reserved dual-purpose configuration pins, but the selected device can contain only <number> output pins

Project requires <number> output pins, including <number> reserved dual-purpose configuration pins, but the selected device can contain only <number> output pins

Project requires <number> SERDES receivers, but the target device can contain only <number> SERDES receivers

Project requires <number> SERDES transmitters, but the target device can contain only <number> SERDES transmitters

Project requires <number> signals of type <type> and <type>, but the selected device can contain only <number> signals of these types

Project requires <number> signals of type <type> and <type>, but the selected device can contain only <number> signals of these types

Project requires <number> signals of type <type> and <type>, but the selected device can contain only <number> signals of these types

Project requires <number> signals of type <type>, <type>, <type>, and <type>, but the selected device can contain only <number> signals

Project requires <number> signals of type <type>, <type>, <type>, and <type>, but the selected device can contain only <number> signals

Project requires <number> signals of type <type>, <type>, and <type>, but the selected device can contain only <number> signals

Project requires <number> signals of type <type>, but the selected device can contain only <number> signals

Project requires <number> signals of type <type>, but the selected device can contain only <number> signals

Project requires <number> signals of type <type>, but the selected device can contain only <number> signals

Project requires <number> signals of type <type>, but the selected device can contain only <number> signals

Project requires <number> signals of type <type>, but the selected device can contain only <number> signals

Project requires <number> XGMII state machines, but the target device can contain only <number> XGMII state machines

Project requires too many <number> ClockLock PLLs, but the selected device can contain only <number> ClockLock PLLs

Project Setting File <name> is read-only and cannot be edited

Project too complex: hierarchy path is too long

Promoted cell <name> to global signal <name>

Promoted logic cell <name> with Global Signal logic option assignment

Promoted PLL clock signals

Promoted signal <name> to use <name>

Promoted signal <name> to use <type> -- fan-outs are assigned to REGION_X<number>_Y<number>_X<number>_Y<number>

Promoted signal <name> to use global clock

Properties dialog box cannot be opened -- multiple programming files are selected in programming list of Programmer window. You must select a single programming file.

Property <name> has an illegal value <number>

Purged intermediate file <name>

Q

Quartus II Archive File <name> already exists -- use the -u or update option to overwrite it, or use another file name

Quartus II Archive File <name> already exists. Do you want to replace it?

Quartus II Help file <name> is missing

Quartus II Help runs only with Internet Explorer software version 5.0 or later

Quartus II software applied gate-level register retiming to <number> clock domains

Quartus II software applied gate-level register retiming to clock <clock name>: created <number> new registers, removed <number> registers, left <number> registers untouched

Quartus II software changed type of port <name> from INTEGER to STD_LOGIC

Quartus II software is resynthesizing <number> WYSIWYG logic cells using the <name> technology mapper and leaves <number> WYSIWYG logic cells untouched

Quartus II Web Edition license file does not support <name> feature

Quartus II software encountered an error while reading SignalTap II File <name>, with message <text>

R

raddr port is not connected in WYSIWYG RAM primitive <name>

Radix contains invalid character(s)

RAM ADDRESS_WIDTH parameter specified for WYSIWYG primitive <name> at port A must operate in deep RAM mode

RAM ADDRESS_WIDTH parameter specified for WYSIWYG primitive <name> at port A must operate in deep RAM mode

RAM ADDRESS_WIDTH parameter specified for WYSIWYG primitive <name> at port B must operate in deep RAM mode

RAM ADDRESS_WIDTH parameter specified for WYSIWYG primitive <name> at port B must operate in deep RAM mode

RAM name is <name>

RAM outputs <name> and <name> are assigned to the same Embedded System Block with Turbo Bit settings that do not match

RAM size configuration exceeded memory block type <type> limit of <number> bits

Raw Binary Files and Tabular Text Files do not support multiple pages

RDYnBSY pin must be assigned the LVTTL I/O standard

Reached breakpoint <name> at time <time>

Reached breakpoint <name> at time <time>

Reached end of document. Do you want to continue searching from start of the document?

Reached end of document. Do you want to continue searching from the start of the document?

Reached end of document. Do you want to continue searching from start of document?

Reached start of document

Reached start of document. Do you want to continue searching from end of the document?

Reached start of document. Do you want to continue searching from the end of the document?

Reached start of document. Do you want to continue searching from end of document?

Reached value breakpoint <name> at time <time>

read clock signal of HSDI synchronizer ATOM <name> must be fed by clkout port of HSDI transmitter ATOM <name>

read enable signal of HSDI synchronizer ATOM <name> must always remain high when it feeds HSDI transmitter

Reading initial Memory Initialization File or Hexadecimal (Intel-Format) File <name>

Ready to acquire

Real-time CRC ERROR_CHECK_FREQUENCY_DIVISOR value in design does not match value in Compiler Settings File

Real-time CRC must be enabled for CRC block

Receiver fast PLL <name> and transmitter fast PLL <name> are merged together

recovclkout output port of GXB receiver channel atom <name> cannot be connected when GXB receiver channel atom <name> is not in channel 0 or is not in channel alignment mode

recovclkout output port of GXB receiver channel atom <name> in channel 0 must be connected to either masterclk input port of GXB receiver channel atom or to recovclk input port of XGMII state machine atom

recovclkout output port of GXB receiver channel atom <name> in channel 0 must be connected when GXB receiver channel atom <name> is in channel alignment mode

Recursive logic detected while extracting entities

Reduced register <name> with stuck <name> port to stuck value <number>

Reduced register <name> with stuck signal <name> to <name>

Reduced registers with stuck control signals

Reevaluating parameters for PLL <name>

Reference clock frequency for HSDI PLL <name> is <text>, but must be within the range of <text> to <text>.

Region <location> corner: <location>; Region <location> corner: <location>

Region <name> is <name>, <name>, location: <name>, size = (<number>,<number>), parent = <name>

Region <name> is assigned <number> nodes or entities of type <type>, but the region can contain only <number> nodes or entities

Region <name> is assigned <number> nodes or entities of type <type>, but the specified cell region can contain only <number> nodes or entities of this type

Region <name> is assigned <number> signals of type <type>, <type>, <type>, <type>, and <type>, but the region can contain only <number> signals of this type

Region <name> is assigned <number> signals of types <type> and <type>, but the region can contain only <number> signals of this type

Region <name> is assigned <number> signals of types <type>, <type>, and <type>, but the region can contain only <number> signals of this type

Region can accept <number> entities of type <type>, but the Fitter needs to place <number> of them in this region

Region with lower-left corner at <number>, <number> and upper-right corner at <number>, <number> requires <number> globally routed signals but can contain only <number> globally routed signals

Register <name> and LVDS transmitter and receiver <name> are not in same MegaLAB structure

Register <name> feeding LVDS transmitter <name> is already used by the LVDS receiver. Add a register to get correct timing.

Register <name> feeding LVDS transmitter <name> should be be fed by a logic cell

Register <name> feeding LVDS transmitter <name> should be fed by a logic cell or ESB

Register <name> following LVDS receiver <name> has an inverted input

Register <name> following LVDS receiver <name> is already used by the LVDS. Add a register to get correct timing.

Register <name> following LVDS receiver <name> must have inverted clock in x4 mode

Register <name> following LVDS receiver <name> should not have inverted clock

Register <name> has more than one fan-out-- LVDS timing requirements may not be met

Register <name> preceding LVDS transmitter <name> should have inverted clock

Register <name> with the following node

Register <name> with the node(s) in the following submessage(s)

Register cascade chain that starts with LCELL atom <name> and that with LCELL atom <name> has length <number>, but exceeds maximum legal length of <number>

Register for port <name> has <name> signal <name>

Register your Quartus II project for the <name> device family to receive future updates and support

Register(s) in WYSIWYG I/O primitive <name> has conflicting parameter setttings -- cannot have both asynchronous reset mode and synchronous reset mode parameters

Registered output is <name>

Registers feeding <DQS I/O or DQ I/O> pin <name> must be driven by clock generated by PLL

Registers feeding the LVDS transmitter <name> does not have the same clock source

Registers with preset signals will power up high

Registers with preset signals will power up high

Regular expression <text> entered is illegal

Release clears before tri-states option turned on. If you are using EP1S25 revision A or B devices, contact Altera Applications.

Remote update block field <text> is set to <value>

Remote update block initial state

Remote update block update register updated at time <time>

Removed LogicLock region assignment <name> from node <name>

Removed LogicLock region assignments -- nodes in carry chain contain both location assignments and LogicLock region assignments

Removed LogicLock region assignments -- nodes in cascade chain contain both location assignments and LogicLock region assignments

Removed LogicLock region assignments -- nodes in DSP block slice contain both location assignments and LogicLock region assignments

Removed LogicLock region assignments from the following nodes

Removed node <name> from LogicLock region <name>

Removed node <name> from LogicLock region <name> -- node has a Fast Input or Output Register assignment

Removed node <name> from LogicLock region <name> -- node is a DQS I/O pin

Removed node <name> from LogicLock region <name> -- node is used for dedicated differential I/O

Removed node <name> from LogicLock region <name> -- node is used for JTAG programming

Removed node <name> from LogicLock region <name> -- node is used to drive an internal global signal

Removed node <name> from LogicLock region <name> -- node used with a PLL

Removed nodes used for dedicated differential I/O from LogicLock regions

Removed Prevent Assignment to LogicLock Regions logic option on node or entity <name>

Removed the following redundant logic cells

Removed the following redundant logic cells

Removed unnecessary TRI buffers in design files -- buffers are permanently enabled

Removing a top-level design entity purges it from the database data for the design entity -- do you want to remove the top-level design entity and purge its data from the database?

Removing OPNDRN node <name> that feeds logic

Replaced illegal text <text> with replacement text <text>

Requirement for fmax must be greater than zero

Reroute the design to continue

Reserve pin type for pin <name> is not supported for the chosen device family.

Reserve pin type for pin <name> is not supported for the chosen device family. Pin will be set to OUTPUT_DRIVING_UNSPECIFIED.

RESERVE_PIN setting for pin <name> has an illegal value

Reserved <number> pins as INPUT mode for potential power pins in device migration

Reserved <number> pins for migration device

Reserved locked LogicLock region <name> overlaps with another locked LogicLock region

Reserved node <name> as a VREF and assigned to regular I/O pin <name>

reset signals of HSDI synchronizer ATOM <name> and its deserializer ATOM <name> are driven by different sources

reset signals of HSDI synchronizer ATOM <name> and its serializer ATOM <name> are driven by different sources

resetall input port of XGMII state machine atom <name> and areset input port of GXB transmitter PLL must be fed by same source

Restoring project from Quartus II Archive File to current project directory will close current project. Do you want to continue?

Result of arithmetic expression (<text>) cannot be negative

Result of arithmetic expression (<text>) cannot be negative

Result of division operation <number>/<number> contains a remainder -- truncated result

Result of expression is not an integer

Result of LOG2 is not an integer -- rounded result to next whole number

Resulting VOD of GXB transmitter channel <name> has value <number> mV that exceeds maximum legal VOD value of <number> mV

Right of Boolean equation cannot contain text <text>

Right of Boolean equation cannot contain text <text>

Ripple clock structure <number> contains <number> node(s)

Routing Constraints File <name> does not exist, using file <name> instead

Routing constraints may not work for virtual I/Os

Routing for this connection is constrained

Routing resource <name>

Row index of location <name> must be <name><name>

Row(s) and heading in table of Truth Table Statement must have equal number of items

Row-global pin is assigned to a row that supports only internal row-global signals

Row-global signal and its destination nodes do not fit in a single row

Row-global signal fans out to nodes that are in multiple rows

Row-global signal is assigned to a non-global location

Row-global signal source fans out to <number> nodes that do not fit in a single row

Row-global signal source is part of carry chain

Row-global signal source is part of counter

Row-global signal source is part of multiplier

Run timing analysis before generating netlist for the selected timing analysis tool

Run timing analysis before generating netlist/output files for the selected EDA tool(s)

Running command-line command <text> after software build

Running command-line command <text> during software build

S

Sample depth is not supported -- using default sample depth

Saved Conversion Setup File <name>

Scalar property <name> cannot be applied to vector net

SCAN_CHAIN parameter of enhanced PLL <name> must be specified when using real-time control of advanced parameters

scanclk port of enhanced PLL <name> is disconnected or is driven by GND or VCC -- scanclk port must be driven by a signal

Scirocco software error: <text>

Scirocco software information: <text>

Scirocco software warning: <text>

SDRAM <number>-bit data width not valid for device <name>

SDRAM <number>-bit data width specified in System Build Descriptor File <name> does not match <number>-bit data width in the design

SDRAM <number>-bit data width specified in the System Build Descriptor File <name> is not valid for device <name>

SDRAM clock frequency may be too slow for SDRAM initialization to be completed within one SDRAM refresh period

Searched to beginning of floorplan. Do you want to search from end?

Searched to end of floorplan. Do you want to search from beginning?

Section <name> in settings and configuration file <name> already contains keyword <name> -- deleting duplicate keyword

Section <name> in settings and configuration file <name> does not require section keyword <name> -- deleting section

Section <name> in settings and configuration file <name> requires a section keyword -- deleting section

Section <name> not a legal section of settings and configuration file <name> -- deleting illegal section

Select a custom hierarchy

Select a device

Select a device

Select a valid simulation tool that can be run automatically from within the Quartus II software

Selected <name> state machine encoding method for state machine <name>

Selected device <name> does not match device type <type> specified in the System Build Descriptor File <name>

Selected device <name> for design <name>

Selected device <name> is supported in current version of the Quartus II software, but support for the device is not installed -- select an installed device

Selected device does not support differential I/O standards

Selected device is in use

Selected device not found

Selected migration device <name> cannot be used for device migration

Selected migration device list is legal with <number> total of migratable pins

Selected migration devices are illegal

Selected option <name> no longer exists in Project Settings File

Selected port is busy

Selected range does not match the range cut or copied to the clipboard

Selected target device is illegal or not supported in this version of the Quartus II software -- turned off device migration

Semantic error in vector source file <name> at line <number>: <text> <text>

SERDES transmitter <name> drives <number> output pins, but must drive only one output pin

SERDES transmitter <name> must drive one output pin

SERDES transmitter <name> must have combination of VCC and GND as input data when used as a transmitter clock output from fast PLL <name>

Serial clock output frequency <number> for GXB receiver PLL of GXB receiver channel atom <name> must be in the frequency range of <number> to <number>

serialdatain input port of GXB transmitter channel atom <name> must be fed by an input pin when slpbk input port is used

serialfdbk input port of GXB receiver channel atom <name> in channel <number> must be fed by dataout output port of a GXB transmitter channel atom in channel <number>

Setting <name> in settings and configuration file <name> is illegal -- deleting illegal setting

Setting for <name> option in Options Statement must be <text>

Setting for BIT0 option in Options Statement must be LSB, MSB, or ANY

Settings and configuration file <name> already contains section <name> -- deleting duplicate section

Settings and configuration file <name> already contains section <name>(<name>) -- deleting duplicate section

Settings and configuration file <name> contains a syntax error that causes an illegal setting -- deleting illegal setting

Settings and configuration file <name> contains a syntax error that causes an illegal setting. The incorrect text is <text> -- deleting illegal setting.

Settings and configuration file <name> does not exist

Settings apply to <name> output files generated for both EDA tool <name> and EDA tool <name> -- do you want to save the changes, overwriting previous tool settings?

Settings for aclr port must be same for wraddress and wren ports in altdpram megafunction

Settings for generating <name> output files apply to both EDA tool <name> and EDA tool <name> -- do you want to save the changes, overwriting previous tool settings?

Settings for generating <name> output files apply to both EDA tool <name> and EDA tool <name> -- do you want to save the changes, overwriting previous tool settings?

Settings name contains an illegal character -- specify a legal settings name

Severity level keyword in Assert Statement is <text>, but must be INFO, ERROR, or WARNING

Shift operator shift amount too wide : shift distance is <number> bits wide, data width is <number> bits

Shift register structure <number> contains <number> node(s)

Signal <name>

Signal <name>

Signal <name> cannot connect to more than one source signal

Signal <name> does not exist in SignalTap II File

Signal <name> in line <number> of Routing Constraints File does not exist

Signal <name> is globally routed to <number> nodes in the region with lower-left corner at <number>, <number> and upper-right corner at <number>, <number>

Signal <name> is globally routed to node <name> in the region with lower-left corner at <number>, <number> and upper-right corner at <number>, <number>

Signal <signal name> driven by an input pin

Signal from combout port of DQS I/O pin <name> does not drive clock input port of its fan-out node <name> -- it must drive the clock input port of a DDIO bidirectional pin, and cannot be routed to core

Signal name <name> changed to enum type

SignalProbe compilation was <successful, NOT successful, stopped, or canceled due to an error>

SignalProbe feature does not support device family <name>

SignalProbe information not saved -- can't perform SignalProbe compilation following smart compilation

SignalProbe pin(s) will be connected

SignalProbe pin(s) will be connected

SignalProbe pin(s) will not be connected

SignalProbe pin(s) will not be connected

SignalProbe routing in progress -- routing <number> pins

SignalProbe routing in progress: routing pin <name> to pin <name>

SignalProbe routing of pin <name> successful

SignalProbe routing successful: successfully routed <number> pins

SignalProbe routing to pin <name> NOT successful

SignalProbe signal error -- <number> of <number> enabled SignalProbe signals could not be routed

SignalProbe source is not specified for <name> -- reserve the pin only

SignalProbe source name <name> already assigned to pin <number> -- a SignalProbe source name cannot be assigned to multiple pins

SignalProbe source name and pin name cannot be the same

SignalTap II data acquisition is in <type> state: <text>

SignalTap II File contains an instance created in a previous version of the Quartus II software. You must update it to compile the current project with the STP File. If you need to acquire data from the SRAM Object File generated in a previous version, make a copy of the file. Do you want to update the file?

SignalTap II File is compatible with the current compiled project -- compilation stopped

SignalTap II File is not in valid format

SignalTap II File requires clock signal

SignalTap II File requires signals

SignalTap II Logic Analyzer data acquisition stopped

SignalTap II Logic Analyzer is not supported for selected device family-- Auto SLD Node Entity section <name> is disabled

Simulation end time <time> did not reach the end of the input vector, which ended at <time>

Simulation ended before power estimation start time

Simulation has paused at time <time>

Simulation has reached breakpoint <name> at <time>

Simulation initialized successfully. Awaiting further instructions.

Simulation is currently running. Simulating design using previous Simulator settings -- changes made to Simulator settings will not take effect until you reinitialize the Simulator.

Simulation is currently running. Simulating design using previous Simulator settings -- changes made to Simulator settings will not take effect until you reinitialize the Simulator.

Simulation is currently running. Simulating design using previous Simulator settings -- changes made to Simulator settings will not take effect until you reinitialize the Simulator.

Simulation is currently running. Simulating design using previous Simulator settings -- changes made to Simulator settings will not take effect until you reinitialize the Simulator.

Simulation is currently running. Simulating design using previous Simulator settings -- changes made to Simulator settings will not take effect until you reinitialize the Simulator.

Simulation results do not match expected results from vector source file <name>

Simulation results do not match expected results from vector source file <name>

Simulation results match expected results from vector source file <name>

Simulation tool launch was successful

Simulation was <successful, NOT successful, stopped, or canceled due to an error>

Simulator is already initialized. Simulating design using previous Simulator settings -- changes made to Simulator settings will not take effect until you reinitialize the Simulator.

Simulator is already initialized. Simulating design using previous Simulator settings -- changes made to Simulator settings will not take effect until you reinitialize the Simulator.

Simulator is already initialized. Simulating the design using previous Simulator settings -- changes made to Simulator settings will not take effect until you reinitialize the Simulator.

Simulator is already initialized. Simulating the design using previous Simulator settings -- changes made to Simulator settings will not take effect until you reinitialize the Simulator.

Simulator is already initialized. Simulating the design using previous Simulator settings -- changes made to Simulator settings will not take effect until you reinitialize the Simulator.

Simulator is already initialized. Simulating the design using previous Simulator settings -- changes made to Simulator settings will not take effect until you reinitialize the Simulator.

Simulator Settings File <name> already exists for another project. If you do not select a different top-level design entity name for the project you are creating, you may lose data from the other project. Do you want to select a different top-level design entity name?

Simulator settings name contains an illegal character -- specify a legal Simulator settings name

Simultaneous write to memory block address <address> at time <time> in vector source file -- data is invalid in memory block

Simultaneous write to same address on Embedded System Block <name> at time <time> -- data will be invalid in ESB

Size of device data exceeds memory capacity of configuration device

Size of file(s) in <Main Block Data or Bottom Boot Data> exceeds memory capacity

Size of LogicLock region <name> is illegal -- height and width must be positive numbers

Size of WHEN group differs from size of CASE group, but the two groups must be the same size

Slack time is <time> between source <pin or register> <name> and destination <pin or register> <name>

Slack time is <time> for clock <name> between source <pin or register> <name> and destination <pin or register> <name>

Slave Binary Image File <name> cannot be read because <text>

Slave Binary Image File does not contain any global options

Slave Binary Image File does not contain any peripherals

Slave Binary Image File is targeting <name> device

Slow Slew Rate logic option is turned off for <name> pin

Slow Slew Rate logic option is turned on for <name> pin

Smart compilation specified to OFF -- SignalProbe information will not be saved

Smart compilation specified to ON -- SignalProbe information will be saved

Smart compilation specified to ON -- SignalProbe information will be saved

Smart compilation turned off -- SignalProbe information will not be saved

Smart recompilation skipped module <name> because it is not required

Socket must contain device

SOF Data item missing input file

SOF Data items must have unique page numbers

softreset input port of GXB receiver channel atom <name> must be fed by the same signal that feeds areset input port of GXB transmitter PLL <name>

softreset input port of GXB transmitter channel atom <name> and areset input port of a GXB transmitter PLL must be fed by the same source

softreset signal on GXB transmitter or receiver channel or resetall signal on XGMII state machine <name> must be same signal as the one driving GXB transmitter PLL areset port in same quad

Software build is in progress. Building software application using previous software build settings -- changes made to software build settings since the software build started will not take effect until you restart the software build.

Software build settings name contains an illegal character -- specify a legal software build settings name

Software build was <successful, NOT successful, stopped, or canceled due to an error>

Software compilation of file <name> was <successful, NOT successful, stopped, or canceled due to an error>

Software toolset <name> not in toolset directory <name> -- specify the toolset directory that contains the software toolset

Some devices in current device list cannot be added to selected programming mode <name>. Do you want to clear all devices in current device list and switch to selected mode?

Some WYSIWYG primitives POWER_UP_HIGH states changed

Source node <name> connects to port <name>

Source of port <name> in JTAG block <name> must be pin

Source or design files have changed. Do you want to recompile before starting HardCopy File Generation?

Source or design files have changed. Do you want to recompile before starting the Design Assistant?

Source or design files have changed. Do you want to recompile before starting the timing analysis?

Source or design files have changed. Do you want to recompile in order to start the simulation?

Source or design files have changed. Do you want to recompile in order to start the software build?

Specified path to locate file <name> uses the Universal Naming Convention (UNC); however, UNC support is not available in the Quartus II software -- specify a path that does not use UNC

Specified path to locate file <name> uses the Universal Naming Convention (UNC); however, UNC support is not available in the Quartus II software -- specify a path that does not use UNC

Specify a <type> file name

Specify a clock settings name

Specify a clock signal name

Specify a Compiler settings name

Specify a Compiler settings name

Specify a file name

Specify a glitch interval

Specify a group name

Specify a legal bus width

Specify a legal clock setting for grid size

Specify a legal end time

Specify a legal end time

Specify a legal end time

Specify a legal font size

Specify a legal offset time

Specify a legal period or phase

Specify a legal start time

Specify a legal start time

Specify a legal time

Specify a legal time interval

Specify a MAX+PLUS II Assignment and Configuration File

Specify a MAX+PLUS II Assignment and Configuration File name

Specify a maximum of 1024 nodes in a SignalTap II instance

Specify a name and valid path for the Compilation focus

Specify a node name

Specify a numeric or named value

Specify a project name, working directory, and top-level design entity

Specify a signal name for GND

Specify a signal name for VCC

Specify a signal that feeds the current node

Specify a SignalTap II File name

Specify a Simulator settings name

Specify a Simulator settings name

Specify a software build settings name

Specify a software build settings name

Specify a software toolset directory

Specify a start index

Specify a test bench design instance name

Specify a test bench entity name

Specify a test bench module name

Specify a value in the <name> field

Specify a value in the <name> field

Specify a Verilog Quartus Mapping File name

Specify a Verilog Quartus Mapping File name

Specify an end time

Specify an existing software toolset directory

Specify an export focus

Specify at least one MAX+PLUS II assignment type to import

Specify at least one MAX+PLUS II assignment type to import

Specify comment text

Specify either a top-level design entity or the full hierarchical path of a lower-level entity as the focus point

Specify programming hardware setup

Specify the command-line options for the preferred text editor. The correct syntax for external editors is described above the box.

Specify values that are greater than or equal to zero

Speed grade of target device is different from speed grade of previously selected migration device

SR latch <number> contains <number> node(s)

SRAM Object File does not have <name> update turned on

Start address 0x<name> ignored for page <page>

Started fitting attempt <number> on <date> at <time>

Starting second synthesis pass using Fitter timing information

State <name> uses code string <text>

State bit <name> of state machine <name> cannot be assigned a value

State bit assignments are not unique for state <name> and state <name>

State machine <name> contains <number> states and <number> state bits

State machine <name> contains no transitions out of state <name>

State Machine <name> has no clock signal

State machine <name> must be reset to ensure proper operation

State machine name <name> must be assigned or compared to state value

State machine name <name> must be assigned or compared to state value

State machine name <name> must be assigned or compared to state value

State must be used in expression that describes state machine

Stratix EP1S10 device selected -- to obtain programming file compatible with ES labeled devices, specify EP1S10ES device

Structure <number> contains <number> node(s)

Structure <number> with different clock edges contains <number> node(s)

Successfully added global option <name> to Slave Binary Image File

Successfully added peripheral <name> to register base address <text> in Slave Binary Image File

Successfully exported data to file <name>

Successfully imported assignments from MAX+PLUS II Assignment and Configuration File <name>

Successfully imported assignments from MAX+PLUS II Assignment and Configuration File <name>

Successfully incrementally routed SignalTap II pre-synthesis nodes

Successfully loaded and ran Tcl Script File <name>

Successfully loaded and ran Tcl Script File <name>

Successfully ran Tcl command <text> specified in Tcl toolbar button number <number>

Successfully removed global option <name> from Slave Binary Image File

Successfully removed peripheral <name> from register base address <text> in Slave Binary Image File

Successfully routed all SignalProbe signals

Support for device <name> not installed -- switching to an appropriate device from the available devices. Altera recommends removing all location assignments when changing the device -- do you want to remove all location assignments?

Support for device family <name> not installed -- switching to device family <name> and choosing an appropriate device from the available devices. Altera recommends removing all location assignments when changing the device -- do you want to remove all location assignments?

Support for IP core <name> in device family <family> is advanced and core functionality has not been fully verified

Support for IP core <name> in device family <family> is preliminary and specifications are subject to change

Switched primary clock for PLL <name> because its clock input pin <name> assigned to I/O pin that does not feed primary clock input port of PLL

Symbol <name> already exists. Do you want to reset all the block's I/Os and parameters with the ones from <name> and erase all current I/Os and parameters?

Symbol <name> already exists. Do you want to reset all the block's I/Os and parameters with the ones from <name> and erase all current I/Os and parameters?

Symbol <name> does not exist in mnemonic table <name>

Symbol <name> has changed. Do you want to update it?

Symbol <name> has duplicate value <name> in mnemonic table <name> -- ignoring new value <name>

Symbolic name <name> already defined as <text>, and cannot be defined again

Symbolic name <name> cannot be defined more than once, and cannot be a reserved keyword

Symbolic name <name> cannot be used for more than one port in Function Prototype <name>

Symbolic name <name> cannot have port

Symbolic name <name> is used as megafunction or macrofunction, but is defined as something other than a megafunction or macrofunction

Symbolic name <name> is used but not defined

Symbolic name <name> is used but not defined

Symbolic name <name> is used but not defined as a dual-range group

Symbolic name <name> is used but not defined as a dual-range group -- attempted to use existing nodes

Symbolic name <name> is used but not defined as a group